- 04 10月, 2013 7 次提交
-
-
由 Andre Przywara 提交于
To enable hypervisors utilizing the ARMv7 virtualization extension on the Versatile Express board with the A15 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the VExpress specific manner. There is no need to provide a custom smp_waitloop() function here. This also serves as an example for what to do when adding support for new boards. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
由 Andre Przywara 提交于
For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
由 Andre Przywara 提交于
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
由 Andre Przywara 提交于
To actually trigger the non-secure switch we just implemented, call the switching routine from within the bootm command implementation. This way we automatically enable this feature without further user intervention. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
由 Andre Przywara 提交于
The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
由 Andre Przywara 提交于
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
由 Andre Przywara 提交于
A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
- 03 10月, 2013 1 次提交
-
-
由 Andre Przywara 提交于
armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
- 02 10月, 2013 2 次提交
-
-
由 Albert ARIBAUD 提交于
-
由 Albert ARIBAUD 提交于
-
- 27 9月, 2013 6 次提交
-
-
由 Eric Nelson 提交于
This patch adds the pad to i.MX6DQ and changes the i.MX6DLS declaration to match the Linux kernel declaration. Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com> Acked-by: NMarek Vasut <marex@denx.de>
-
由 Pierre Aubert 提交于
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: NPierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: NEric Nelson <eric.nelson@boundarydevices.com>
-
由 Fabio Estevam 提交于
If smc911x_initialize() fails we should return the error immediately. While at it, also check the error from cpu_eth_init(). Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
-
由 Fabio Estevam 提交于
If cpu_eth_init() fails we should return the error immediately. Cc: Marek Vasut <marex@denx.de> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NMarek Vasut <marex@denx.de>
-
由 Fabio Estevam 提交于
If cpu_eth_init() fails we should return the error immediately. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 York Sun 提交于
Convert set_hdr_func(struct imx_header *imxhdr) to set_hdr_func(void) to get rid of the warning warning: ‘imxhdr’ is used uninitialized in this function Signed-off-by: NYork Sun <yorksun@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
-
- 24 9月, 2013 2 次提交
-
-
由 Jeroen Hofstee 提交于
Besides the change of this patchset it also updates the README to reflect that GOT-generated relocations are no longer supported on ARM. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
-
由 Jeroen Hofstee 提交于
To be more EABI compliant and as a preparation for building with clang, use the platform-specific r9 register for gd instead of r8. note: The FIQ is not updated since it is not used in u-boot, and under discussion for the time being. The following checkpatch warning is ignored: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
-
- 23 9月, 2013 4 次提交
-
-
由 Jeroen Hofstee 提交于
r9 is a platform-specific register in ARM EABI and not per definition a general purpose register. Do not use it while relocating so it can be used for gd. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
-
由 Masahiro Yamada 提交于
Every ARM cpu config.mk (arch/arm/cpu/{CPUDIR}/config.mk) defines: PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float So, this patch moves the common compiler options to arch/arm/config.mk. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
-
由 Michal Simek 提交于
Reload address was written to the counter register instead of load register. The problem happens when timer expires but never reload to ~0UL (it is downcount timer). Reported-by: NStephen MacMahon <stephenm@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Jeroen Hofstee 提交于
The movt/movw instruction can be used to hardcode an memory location in the instruction itself. The linker starts complaining about this if the compiler decides to do so: "relocation R_ARM_MOVW_ABS_NC against `a local symbol' can not be used" and it is not support by U-boot as well. Prevent their use by requiring word relocations. This allows u-boot to be build at other optimalization levels then -Os. Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Cc: TigerLiu@viatech.com.cn Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: NSimon Glass <sjg@chromium.org>
-
- 21 9月, 2013 6 次提交
-
-
由 Robert P. J. Day 提交于
If, in CONFIG_BOOTCOMMAND, the environment switches both the mmcdev and bootpart variables to refer to MMC device 1, it would make sense that the mmcroot env variable should switch to that device as well. Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
-
由 Heiko Schocher 提交于
if phy_connect() did not find a phy, phydev is NULL and following code in cpsw_phy_init() crashes. Fix this. Signed-off-by: NHeiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: NMugunthan V N <mugunthanvnm@ti.com>
-
由 Lokesh Vutla 提交于
Writing magic bits into LDO SRAM was suggested only for OMAP5432 ES1.0. Now these are no longer applicable. Moreover these bits should not be overwritten as they are loaded from EFUSE. So avoid writing into these registers. Boot tested on OMAP5432 ES2.0 Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
-
由 Lokesh Vutla 提交于
dra7xx_evm has eMMC and the default environment can be stored in it. So enabling saveenv command and the configs to store environment in eMMC. Tested on DRA752 ES1.0 Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
-
由 Steve Kipisz 提交于
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: NSteve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: NTom Rini <trini@ti.com>
-
由 Tom Rini 提交于
Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: NTom Rini <trini@ti.com>
-
- 20 9月, 2013 12 次提交
-
-
由 Fabio Estevam 提交于
Performing tftp transfers on mx28 results in random timeouts. Hector Palacios and Robert Hodaszi analyzed the root cause being related to the wrong alignment of the 'buff' buffer inside fec_recv(). Benoît Thébaudeau provided an excellent analysis of the alignment bug that is present on older versions, such as GCC 4.5.4: http://marc.info/?l=u-boot&m=137942904906131&w=2 Use ALLOC_CACHE_ALIGN_BUFFER() to avoid alignment issues from older GCC versions. Reported-by: NHector Palacios <hector.palacios@digi.com> Tested-by: NOliver Metz <oliver@freetz.org> Tested-by: NHector Palacios <hector.palacios@digi.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NMarek Vasut <marex@denx.de> Tested-by: NMarek Vasut <marex@denx.de>
-
由 Fabio Estevam 提交于
We need to load 'imx6dl-sabresd.dtb' in the mx6dl version. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Fabio Estevam 提交于
Since commit bce88370 (ARM: mxs: tools: Add mkimage support for MXS bootstream) the following build error is seen when doing a MAKEALL build: $ ./MAKEALL mx28evk Configuring for mx28evk - Board: mx28evk, Options: ENV_IS_IN_MMC mxsimage.c:18:25: fatal error: openssl/evp.h: No such file or directory Add an entry about the need of installing the 'libssl-dev' package. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NMarek Vasut <marex@denx.de>
-
由 Fabio Estevam 提交于
Fix the following checkpatch warning: $ ./tools/checkpatch.pl -F board/freescale/mx28evk/mx28evk.c CHECK: Alignment should match open parenthesis #109: FILE: freescale/mx28evk/mx28evk.c:109: + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Eric Nelson 提交于
This patch fixes a regression introduced by commit 87d720e0. Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Fabio Estevam 提交于
mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
Similarly as mx25 and mx53, mx6solo-lite needs to setup the MII gasket for RMII mode. Add support for mx6solo-lite. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
Currently board_eth_init() always return 0, but we should propagate the error when cpu_eth_init() fails. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
In arch/arm/cpu/arm1136/cpu.c we have: #ifndef CONFIG_SYS_CACHELINE_SIZE #define CONFIG_SYS_CACHELINE_SIZE 32 #endif ,so there is no need to define 'CONFIG_SYS_CACHELINE_SIZE' with the default size in the board config file. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
malloc can fail, so we should better check its return value before using it. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
If a HDMI cable is not connected, the following message is seen on boot: CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR Board: MX6-SabreSD DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 No panel detected: default to HDMI unsupported panel HDMI Reset the 'i' variable to fix the 'unsupported panel' message. This follows the same idea of commit 47ac53d7 (imx: nitrogen6x/mx6qsabrelite: Fix bug in board_video_skip). Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-