The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Tidy up three minor problems in this file.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: NYork Sun <yorksun@freescale.com>

This SPI controller can only write 64 bytes at a time. Add this restriction
in so that 'sf write' works correct for blocks larger than 64 bytes.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This supports Intel ICH7/9. The Intel controller is a little unusual in
that it is mostly intended for use with SPI flash, and has some
optimisations and features specifically for that application. In
particular it is not possible to support ongoing transactions that
continue over many calls with SPI_XFER_BEGIN and SPI_XFER_END.

This driver supports writes of up to 64 bytes at a time, the limit
for the controller. Future work will improve this.
Signed-off-by: NBernie Thompson <bhthompson@chromium.org>
Signed-off-by: NDuncan Laurie <dlaurie@chromium.org>
Signed-off-by: NBill Richardson <wfrichar@chromium.org>
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>