The CONFIG_CMD_ENV is enabled by default so we can safely remove it.
Signed-off-by: NLuka Perkov <luka.perkov@sartura.hr>

Avoid double typing in the shell and build u-boot.kwb when running "make" only.
Signed-off-by: NLuka Perkov <luka.perkov@sartura.hr>

Mainline kernel for this device has only support for device tree. We can safely
drop this legacy code.
Signed-off-by: NLuka Perkov <luka.perkov@sartura.hr>

Create include/configs/mv-plug-common.h for common definitions
for Sheevaplug, Guruplug and Dreamplug. This will make it easier
to ensure the built u-boots stay in track with each other
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

CONFIG_DISPLAY_CPUINFO is already defined in mv-common.h
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

Cosmetic: CONFIG_OF_LIBFDT was in a different position in the config
file for the Dreamplug, compared to the Sheevaplug and Guruplug.
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

include/configs/mv-common.h brings in the required filesystems if
CONFIG_SYS_MVFS is defined, so use it for Sheevaplug and Guruplug.
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

For Marvell plugs, move the configuration of DHCP, NAND/SF, PING
and USB commands, and HUSH_PARSER into the _defconfig file, rather
than the include/configs/*plug.h files.

This avoids compiler warnings of duplicate definitions if the
option is selected in the .config, but also defined in the
include/configs/*plug.h file.
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

include/configs/guruplug.h defined CONFIG_CMD_FAT twice.
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

The Marvell plugs are very similar systems, and so it makes sense
for their u-boots to have the same commands/configuration.

Add EXT4 and MII to Dreamplug, DATE to Guruplug and Sheevaplug.
Add CONFIG_SYS_ALT_MEMTEST to Sheevaplug.
There are still command differences around NAND, SPI/NOR.

Also default to building u-boot.kwb for Sheevaplug and Guruplug.
Signed-off-by: NQuentin Armitage <quentin@armitage.org.uk>

SAR1_CPU_CORE_MASK was wrong, probably copy/paste
from another architecture.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NStefan Roese <sr@denx.de>

The binary header ends with one lword, defining if another header
follows this one. This additions 4 bytes need to be taken into
account in the generation of the header size. And the complete
4 bytes at the end of this binary header need to get cleared.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>

Instead of allocating space in the driver for the serdes
specification table, just allow the board file to set a pointer
to it.  Also, allow the board to only specify the lanes that are
used instead of including unused lanes.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: NStefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Functions that do not modify the pointer passed should declare it
as const.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: NStefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support.  Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM.  If this needs to be done, it should be
handled in the board file, not in core code.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: NStefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Signed-off-by: NTom Rini <trini@konsulko.com>

The read_trace_config() can dereference the line pointer after freeing
it on its error path. Avoid that.

This was found by Coverity Scan.
Signed-off-by: NVincent Stehlé <vincent.stehle@freescale.com>
Cc: Simon Glass <sjg@chromium.org>

Add the following splash locations to cm-fx6:
* filesystem formatted mmc
* filesystem formatted usb
* filesystem formatted sata

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

Add support for loading splashimage from filesystem formatted sata
storage.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>

Add support for loading splash image from USB drive formatted with a
filesystem.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>

Add support for loading splash image from an SD card formatted with
a filesystem. Update boards to maintain original behavior where needed.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>

Rename raw read functions to *_read_raw() in preparation for supporting
read_fs() feature.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

commit c3c016cf "sf: Add SPI NOR protection mechanism" introduced
flash_lock()/flash_unlock()/flash_is_locked() methods for SPI flash,
but not every flash driver supplies these. We should test these
methods against NULL before actually calling them.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver
model, PCI enumeration is automatically triggered.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that we have converted all x86 boards to use driver model pci,
remove these legacy pci codes.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

These are leftover when converted to use driver model pci.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move to driver model for ETH (e1000) on QEMU.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move to driver model for USB on QEMU.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move to driver model for pci on QEMU.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Move chipset-specific codes such as PAM init, PCIe ECAM and MP table
from pci.c to qemu.c, to prepare for DM PCI conversion.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The call to pci_run_vga_bios() is not needed as this is handled
in the vesa_fb driver.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Currently timer_init() is called in board_r.c which is quite late.
Some vgabios execution requires we set up the i8254 timer correctly,
but video initialization comes before timer_init(). Move the call
to board_f.c.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.

However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.

To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add Kconfig options for 8259 and 8254.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Initialize counter 1, used to refresh request signal. This is
required for legacy purpose as some codes like vgabios utilizes
counter 1 to provide delay functionality.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This cleans up i8254 and i8259 codes to fix several cosmetic
issues, like coding convention and some comments improvement.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>