Initial ground work in preperation for generic board initialization
code for the SPARC architecture.
Signed-off-by: NFrancois Retief <fgretief@spaceteq.co.za>

Signed-off-by: NFrancois Retief <fgretief@spaceteq.co.za>

Updated the LEON3 serial driver to make use of the CONFIG_CONS_INDEX
option to select which serial port the console will use.
Signed-off-by: NFrancois Retief <fgretief@spaceteq.co.za>

Signed-off-by: NDaniel Hellstrom <daniel@gaisler.com>

Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the
panic function can use DEBUG_UART driver. drivers/serial/serial.c set this
flag before calling this function, preventing DEBUG_UART code from running.
Signed-off-by: NFrancois Retief <fgretief@spaceteq.co.za>

Signed-off-by: NDaniel Hellstrom <daniel@gaisler.com>

Remove the version_string variable from start.S file. A weak variable
is also set in the cmd_version.c file. No need for architecture override.
Signed-off-by: NFrancois Retief <fgretief@spaceteq.co.za>

Signed-off-by: NFrancois Retief <fgretief@spaceteq.co.za>

In order to fit into image constraints again, remove this feature.
Signed-off-by: NTom Rini <trini@konsulko.com>

Now that u-boot relocates the malloc area in SPL to SDRAM, with the
malloc area sitting below the SPL_STACK_R_ADDR the
SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for
rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then
STACK_R_MALLOC_SIMPLE_LEN (1Mb).

Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot
from SD card.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

This patch was merged shortly before the v2015.10 as a minimal fix for
booting on rockchip. Now that the patch series from Hans to do the
relocation in generic code has been merged it can be dropped.

This reverts commit b1f492ca.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

Commit 1eb0c03c added
SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is
evaluated.

Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.

This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.
Signed-off-by: NAriel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: NSimon Glass <sjg@chromium.org>

show how to packet rk3036 uboot image and boot from SD
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Series-to: u-boot
Series-version: 8
Series-cc: Lin Huang <hl@rock-chips.com>

The Rockchip boot ROM could load & run an initial spl loader,
and continue to load a second level boot-loader(which stored
right after the initial loader) when it returns.
Modify idblock generation code to support it.
Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Our chips may have different max spl size and spl header, so
we need to add configs for that.
Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
Added $(if...) to tools/Makefile to fix widespread build breakage
Signed-off-by: NSimon Glass <sjg@chromium.org>

Series-changes: 8
- Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
- Add $(if...) to tools/Makefile to fix widespread build breakage

This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Series-changes: 8
- moved board Kconfig fragment from previous patch into this one

rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288

add rk3036 sdram driver so we can set up sdram in SPL
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

add early uart driver so we can print debug message in
SPL stage
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

rk3036 mmc do not have internal dma, so we use fifo mode when read
and write data, we get the fifo mode and fifo depth property from
dts, pass to dw_mmc driver.
Signed-off-by: NLin Huang <hl@rock-chips.com>

emmc and sdcard have different register address, use non-removeable property
to distinguish them.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

the data transfer seem to long in the dwmci_send_cmd function,
so move this block as a separate funciton.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add a driver which support pin multiplexing setup for rk3036
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add a driver that provides access to system controllers
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

We can reset the Soc using some CRU (clock/reset unit) register.
Add support for this.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

GRF is the gereral register file. Add header files with register definitions.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add a driver for setting up and modifying the various PLLs, peripheral
clocks and mmc clocks on RK3036
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can
remove from SPL stage.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

since different rockchip soc need different spl file,
so rename board-spl.c.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

since different rockchip SOC have different size of SRAM,
So the size SYS_MALLOC_F_LEN may different, so move this
config to rk3288 own Kconfig
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Save the environment on the SD card for Firefly in the empty space
between the SPL and the u-boot image.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>

We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Adjust this command to use the correct PCI functions, instead of the
compatibility layer.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

We want to share this code with the driver model version, so put it in a
separate function.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>