Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

AP325RXA is SH7723's reference board.
This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other.
In this patch, support SCIF, NOR Flash, and Ethernet.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Renesas SH7723 has 5 SCIF, SD, Camera, LCDC and other.
This patch supports CPU register's header file and SCIF serial driver.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This adds initial support for the RTE RSK+ SH7203 board.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add support SH2/SH2A basic function.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This board has SH7785, 512MB DDR2-SDRAM, NOR Flash,
Graphic, Ethernet, USB, SD, RTC, and I2C controller.

This patch supports the following functions:
 - 128MB DDR2-SDRAM (29-bit address mode only)
 - NOR Flash
 - USB host
 - Ethernet
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Renesas SH7785 has DDR2-SDRAM controller, PCI, and other.
This patch supports CPU register's header file.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This function is needed for the new NAND infrastructure. We only need
a dummy implementation though for the NDFC.
Signed-off-by: NStefan Roese <sr@denx.de>

This is needed since now with HUSH enabled (amcc-common.h) the image
read from NAND exceeds the previous limit.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

Made NAND bank configuration setting a config variable.
Signed-off-by: NWolfgang Ocker <weo@reccoware.de>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes a UIC external_interrupt hang if critical or non-critical
interrupt is set at the same time as a normal interrupt is set on UIC0.
Signed-off-by: NVictor Gallardo <vgallardo@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Removed Magic numbers from Initialization preload registers
Tested with Kilauea, Glacier, Canyonlands and Katmai boards
About 5-7% improvement seen for LMBench memtests
Signed-off-by: NProdyut Hazarika <phazarika@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.

The default is to assert CS together with ALE.  The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.

The default is wrong for the NOR flash and CPLD on the ADS5121.

This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.
Signed-off-by: NMartha J Marx <mmarx@silicontkx.com>
Signed-off-by: NJohn Rigby <jrigby@freescale.com>

The existing I2C freqency dividers for FDR does not apply
to ColdFire platforms; thus, a seperate table is added
based on MCF5xxx Reference Manual
Signed-off-by: NLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: NTabi Timur <timur@freescale.com>

Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Add FEC pin set and mii reset in __mii_init(). Change
legacy flash vendor from 2 to AMD LEGACY (0xFFF0),
change cfi_offset to 0, and change CFG_FLASH_CFI to
CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and
M54455EVB env settings in configuration file.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

The user manuals recommend 7.
Signed-off-by: NKurt Mahan <kmahan@freescale.com>
Acked-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

M5249EVB, M5271EVB, M5272C3, M5275EVB and M5282EVB platforms
uart baudrate increase from 19200 to 115200 bps
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Implicit declaration of nand_init() warning message
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NHeiko Schocher <hs@denx.de>

For some reason we duplicated the majority of code in lib_ppc/interrupts.c
not show how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NSrikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: NDejan Minic <minic@freescale.com>
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NSrikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: NDejan Minic <minic@freescale.com>
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NDave Liu <daveliu@freescale.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

All 85xx boards have been converted to the new code so we can
remove the old SPD DDR setup code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>