- 25 5月, 2013 25 次提交
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由 Shaohui Xie 提交于
Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in eth port enum structure, it will assign mdio mux depend on this assumption. This is not true with Fman V3, which added more 1G ports after port DTSEC5 in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux. So we use dynamic index for 10G ports instead of hardcoded enum value when doing mdio mux for 10G ports. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Poonam Aggrwal 提交于
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Xie Xiaobo 提交于
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters. Signed-off-by: NXie Xiaobo <X.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaveta Leekha 提交于
Crossbar switches were wrongly programmed to route the CPRI lanes to SFP as the connectivity table was not correct. Modified it correctly for SFPs connections. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shengzhou Liu 提交于
QSGMII card has different PHY address against previous SGMII card. We check the type of card in slots and set correct PHY address to avoid complainning "PHY reset timed out" during u-boot booting up. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Suresh Gupta 提交于
- Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen George 提交于
Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: NStephen George <stephen.george@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ed Swarthout 提交于
Use QIXIS measurement registers to obtain sysclk and ddr clock. This allows using non-standard clock speeds, set by directly writing to clock chip or store the values in qixis clock data eeprom. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ed Swarthout 提交于
QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 James Yang 提交于
This is compile-time config. Signed-off-by: NJames Yang <James.Yang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
"cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 James Yang 提交于
Signed-off-by: NJames Yang <James.Yang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Add board detail function to print more individual board information. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 24 5月, 2013 2 次提交
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由 Masahiro Yamada 提交于
The "cp" command has not worked since commit 0628ab8e, because of the following lines, which set the destination and the source to the same address. buf = map_sysmem(addr, bytes); src = map_sysmem(addr, bytes); Tested-by: NTom Rini <trini@ti.com> Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Stephen Warren 提交于
Commit 50ce4c07 "fs/ext4: Support device block sizes != 512 bytes" modified ext4fs_set_blk_dev() to calculate total_sect based on get_fs()->dev_desc->log2blksz rather than SECTOR_SIZE. However, this value wasn't yet assigned. Move the assignment earlier so the code doesn't crash or hang. Cc: Egbert Eich <eich@suse.com> Tested-by: NTom Rini <trini@ti.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 23 5月, 2013 3 次提交
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由 Masahiro Yamada 提交于
When base address given was out of valid flash address ranges, flash_get_info() function returned the pointer to the last element of flash_info[i] array. This patch changes this function to return NULL pointer in such a case, which is more correct behaviour. The function flash_protect_default() calls flash_protect() immediately after flash_get_info() invocation. With this correction, flash_protect() function would be able to return soon, for NULL flash_info. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Masahiro Yamada 提交于
Linux Kernel Documentation/CodingStyle says: Do not add a space after unary operators such as &, *, ... Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Andrew Gabbasov 提交于
Packed structure cfi_qry contains unaligned 16- and 32-bits members, accessing which causes problems when cfi_flash driver is compiled with -munaligned-access option: flash initialization hangs, probably due to data error. Since the structure is supposed to replicate the actual data layout in CFI Flash chips, the alignment issue can't be fixed in the structure. So, unaligned fields need using of explicit unaligned access macros. Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com> Reviewed-By: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: NStefan Roese <sr@denx.de>
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- 18 5月, 2013 5 次提交
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由 Simon Glass 提交于
This currently has no maintainer listed. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This still shows the previous maintainer. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Doug Anderson 提交于
It appears that there are some cases where we have more than 4 banks of memory. Use CONFIG_NR_DRAM_BANKS if it's defined to handle this. This will take up a little extra stack space (64 bytes extra if we go up to 8 banks), but that seems OK. Signed-off-by: NDoug Anderson <dianders@chromium.org>
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由 Doug Anderson 提交于
This makes fixup_silent_linux() use malloc() to allocate its working space, meaning that our maximum kernel command line should only be limited by malloc(). Previously it was silently overflowing the stack. Note that nothing about this change increases the kernel's maximum command line length. If you have a command line that is >256 bytes it's up to you to make sure that kernel can handle it. Signed-off-by: NDoug Anderson <dianders@chromium.org> Acked-by: NMike Frysinger <vapier@gentoo.org>
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- 16 5月, 2013 3 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Haijun.Zhang 提交于
The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92 drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Kuo-Jung Su 提交于
Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: NKuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 15 5月, 2013 2 次提交
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由 Wolfgang Denk 提交于
The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: NWolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
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