The generic timer count is an incrementing 64bit value and a timer driver
must return an incrementing 64bit value. The DW APB timer only provides a
32bit timer counting down, thus the result must be inverted and converted
to a 64bit value. The current implementation is however missing the 64bit
up-conversion and this results in random timer roll-overs, which in turn
triggers random timeouts throughout the codebase.

This patch adds the missing 64bit up-conversion to fix the issue.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Merge qspi dts node from Linux.
Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10)

Add -u-boot.dtsi files for non Linux dts properties and
update properties for Uboot.
- add u-boot,dm-pre-reloc
- add alias for spi0
- change compatible for flash
- support quad read and quad write
- change maximum frequency to 100MHz

Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Scrub memory content if ECC is enabled and it is not
from warm reset boot.

Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add helper function cpu_has_been_warmreset() to check
if CPU is from warm reset boot.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

The stratix10 socdk ships with 4GB of memory.  Modify the
device tree to represent this.  Note that to access 4GB of
memory in Stratix 10, due to the IO space from 2GB to 4GB,
we use the fact that the DDR controller ignores upper address
bits outside of the configured DRAM's size.  This means that
, the 4GB DRAM is mapped to memory every 4GB.

For an 8GB memory, you can either live with the 2GB IO space,
and loose access to that memory from the processor, or use
the same trick:

Loose 2GB of memory:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* last 4GB */
                      <1 0x00000000 1 0x00000000>;
                u-boot,dm-pre-reloc;
        };

or to map it all:
        memory {
                device_type = "memory";
                /* 8GB */
		/* first 2GB */
                reg = <0 0x00000000 0 0x80000000>,
		/* next 6GB */
                      <2 0x80000000 1 0x80000000>;
                u-boot,dm-pre-reloc;
        };
Signed-off-by: NDalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Stratix10 maps dram in 2 address spans, from 0-2GB and from
2GB up to 128GB.
Signed-off-by: NDalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Stratix 10 maps dram from 0 to 128GB.  There is a 2GB hole
in the memory for peripherals and other IO from 2GB to 4GB.
However the dram controller ignores upper address bits for
smaller dram configurations.  Example: a 4GB dram
maps to multiple locations, every 4GB on the address.
Signed-off-by: NDalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Move SDRAM size check to SDRAM driver. sdram_calculate_size()
is called in SDRAM initialization already, avoid calling
twice in size check function.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

This commit removes ad-hoc reset handling for peripheral resets from SPL
for socfpga gen5.

This is done because as U-Boot drivers support reset handling by now.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

This adds reset handling to the cadence qspi driver.

For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

This adds reset handling to the devicetree-enabled Denali NAND driver.

For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.

This gets us rid of one ad-hoc call to socfpga_per_reset().

The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.

SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

This adds code to take peripherals out of reset based on an environment
variable. This is in preparation for removing the code that does this from
SPL.

However, some drivers even in current Linux cannot handle peripheral reset,
so until this works, we need a compatibility workaround.

This workaround is implemented in the 'assert' and 'remove' callbacks of
this reset driver: the 'assert' callback does not disable peripherals that
were already taken out of reset, while the 'remove' callback, which is
called on OS_PREPARE, deasserts all peripheral resets if the environment
variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5
SPL did up to now.

This is in preparation to clean up the SPL and implementing proper reset
handling for U-Boot.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

To keep the current behaviour of taking all peripherals out of reset
before booting the OS before removing that code from socfpga gen5 SPL,
this enables the new behaviour by default for all gen5 boards by adding
the environment variable "socfpga_legacy_reset_compat=1" to the default
environment.

This can be overridden in board config files or by saving an environment
without this variable enabled.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

The only member of this driver's priv struct is a pointer, which is
called 'membase'. However, since this driver handles multiple sub-
architectures, this is not the base address from dts but the base
address of some common registers of those sub-arches.

Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.

In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.

This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

This is again a sync to linux-next + pending patches in Dinh's tree at
commit 1c909b2dfe6a ("ARM: dts: socfpga: update more missing reset
properties")'

It adds missing peripheral reset properties to socfpga.dtsi and removes
U-Boot specific leftovers from socfpga_cyclone5_socrates.dts.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Move to DM
-----------

- DM support in sata
- Toradex Board to DM
- wandboard to DM
- tbs2910 to DM
- GE boards to DM
- VHybrid boards to DM
- DM_VIDEO for i.MX

Pull request for UEFI sub-system for v2019.07-rc1 (2)

In the aarch64 crash dump information about the loaded EFI images is added.

In README.uefi the development target is for the UEFI subsystem is
described as "Embedded Base Boot Requirements (EBBR) Specification"
compliance.

Several bug fixes are supplied.

- optional backlight PWM polarity config via polarity cell
- bug fix for ASCII characters > 127
- ANSI sequence handling extensions (implement clear line,
  reverse video and relative cursor movement commands)
- preparation for doing character set translations
- left/right and up/down arrow keys translation to ANSI
  control sequences for cursor movement to fix selection
  with an USB keyboard in bootmenu
- CONFIG_SYS_WHITE_ON_BLACK font scheme configuration for
  sunxi boards

This fixes the build failure "u-boot.imx exceeds file size limit".
Signed-off-by: NSoeren Moch <smoch@web.de>

In the sunxi-common.h config header we unconditionally define
CONFIG_SYS_WHITE_ON_BLACK, although it's actually a Kconfig option which
could be individually selected by a user.
Remove this #define from the header and let it default to "y" on sunxi
boards (like we do for other platforms).
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

So far arrows key pressed on an USB keyboard got translated to some
low ASCII control sequences (Ctrl+N, Ctrl+P). Some programs understand
these codes, but the standard for those keys is to use ANSI control
sequences for cursor movement (ESC [ A).
Our own boot menu is a victim of this, currently we cannot change the
selection with an USB keyboard due to this.

Since we already implement a queue for USB key codes, we can just insert
the three character ANSI sequence into the key buffer. This fixes the
bootmenu, and is more universal for other users (UEFI) as well.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

In preparation for doing character set translations, factor out the
actual glyph display functionality into a separate function.
This will be used in a subsequent patch.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

There is a standard ANSI terminal escape sequence to clear a whole line
of text. So far the DM_VIDEO console was missing this code.

Detect the sequence and use vidconsole_set_row with the background
colour to fix this omission.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The ANSI terminal escapce sequence standard defines relative cursor
movement commands (ESC [ A-F). So far the DM_VIDEO console code was
ignoring them.

Interpret those sequences and move the cursor by the requested amount of
rows or columns in the right direction. This brings the code on par with
the legacy video console driver (cfb_console).
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The video console for DM_VIDEO compliant drivers only understands a very
small number of ANSI sequences. First and foremost it misses the "reverse
video" command, which is used by our own bootmenu command to highlight
the selected entry.

To avoid forcing people to use their imagination when using the
bootmenu, let's just implement the rather simple reverse effect. We need
to store the background colour index for that, so that we can
recalculate both the foreground and background colour pixel values.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
[agust: merged BG color escape seq change to fix "ut dm video_ansi" test]
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

When the character to be printed on a DM_VIDEO console is from the
"extended ASCII" range (0x80 - 0xff), it will be treated as a negative
number, as it's declared as a signed char. This leads to negative array
indicies into the glyph bitmap array, and random garbled characters.

Cast the character to an unsigned type to make the index always positive
and avoid an out-of-bounds access.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch enables the reading of the polarity cell from a PWM
phandle and calls pwm_set_invert().

Not all platforms have polarity cell, so skip if it's not pressent.
Signed-off-by: NStefan Mavrodiev <stefan@olimex.com>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Conflicts:
	arch/arm/dts/armada-385-amc.dts
	arch/arm/dts/armada-xp-theadorable.dts
	arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
Signed-off-by: NTom Rini <trini@konsulko.com>

Enable CONFIG_AHCI to fix errors:
drivers/ata/dwc_ahsata.c: In function `ahci_init_one':
drivers/ata/dwc_ahsata.c:868:21: error: `struct blk_desc' has no member named `priv'
sata_dev_desc[pdev].priv = uc_priv;
     ^
drivers/ata/dwc_ahsata.c: In function `init_sata':
drivers/ata/dwc_ahsata.c:891:30: error: `struct blk_desc' has no member named `priv'
uc_priv = sata_dev_desc[dev].priv;
...

Also enable DM_SCSI to fix migration build warning.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

Fix broken build:
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

Fix broken build:
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

Add device trees to Makefile to avoid newly introduced error:

Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument

make[1]: *** [dts/Makefile:28: arch/arm/dts/imx6-apalis.dtb] Error 1
make: *** [Makefile:1009: dts/dt.dtb] Error 2
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>

ipu.h header is not found since the ipuv3 driver was moved to
the drivers/video/imx subdirectory. Fix it.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

Fix toradex_modules array off by one issue potentially leading to
spurious printout during boot e.g.

    Model: Toradex  V1.2A,

instead of

    Model: Toradex UNKNOWN MODULE V1.2A.
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: NMax Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: NIgor Opaniuk <igor.opaniuk@toradex.com>

If the config block is missing, various things may fail or behave
strangely on certain modules. This patch unifies that behaviour by
using a fake MAC address, until user updates the config block.
Signed-off-by: NBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: NIgor Opaniuk <igor.opaniuk@toradex.com>

Add an optional -y parameter to 'cfgblock create’ to simplify
automation.
Signed-off-by: NDominik Sliwa <dominik.sliwa@toradex.com>
Acked-by: NStefan Agner <stefan.agner@toradex.com>
Acked-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: NIgor Opaniuk <igor.opaniuk@toradex.com>

Currently, Vybrid's sdboot variable tries to load the kernel from /boot
of the root partition (typically second partition when using the sdcard
image). However, since we moved to flash the kernel in a separate UBI
volume, we no longer deploy the kernel/device tree to /boot, hence
sdboot does not work in its current state.

Load the kernel and device tree from the first (typically FAT) partition
as customary on all Toradex modules.

While at it also change from rw to ro as e.g. systemd will re-mount the
root file system rw anyway after checking it.
Signed-off-by: NGerard Salvatella <gerard.salvatella@toradex.com>
Acked-by: NStefan Agner <stefan.agner@toradex.com>
Acked-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: NIgor Opaniuk <igor.opaniuk@toradex.com>

The DDR validation tool (which is part of Processor Expert) allows
to evaluate leveling parameters for CR105/CR106/CR110. Several
runs have been made with Colibri VF50 and VF61 and it seems to
evaluate very similar values. Use this values by default.

Note: The newly evaluated parameters seem to require CTLUPD_AREF
to be enabled!

Note 2: The tool also evaluated 6 as a new value for PHY02/18
GATE_CFG (Coarse adjust of gate open time). However, this seems
not to work in practise.
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
Acked-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>