- 25 7月, 2015 3 次提交
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由 Hans de Goede 提交于
Start using the new Kconfig options which are available for these now, and simply always enable them by selecting them as sunxi builds always include USB support. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
With certain features being convert to DM now we want sunxi to default to having DM enabled for ETH/SERIAL and USB in some cases. Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: NTom Rini <trini@konsulko.com> [hdegoede@redhat.com: Also select CONFIG_USB for all sunxi builds] Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Hans de Goede 提交于
At one point in time the utoo-p66 dts file in the kernel had a bogus uart entry, and it seems like we synced with the kernel at just the wrong moment. This commit removes the bogus uart entry, which breaks booting the utoo-p66 when DM_SERIAL=y. Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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- 24 7月, 2015 2 次提交
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由 Daniel Kochmański 提交于
Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND memory and SD card. Detection where SPL was read from is implemented in `spl_boot_device`. Signed-off-by: NDaniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Some small coding style fixes] Acked-by: NHans De Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Daniel Kochmański 提交于
This patch extracts checking for valid SD card "eGON.BT0" signature from `board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`. Buffer for mmc sector is allocated and freed at runtime. `panic` is triggered on malloc failure. Signed-off-by: NDaniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0] Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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- 23 7月, 2015 12 次提交
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由 Masahiro Yamada 提交于
This I2C device is used SoC-internally for controlling the DMD core. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The init code for UMC (Unified Memory Controller) and PLL has not been mainlined yet, but U-boot proper should work. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
For the record, describe exactly which device of which vendor is used on this board. I2C EEPROM is bound by the generic compatible string, "i2c-eeprom", so this commit has no impact on the functionality. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Stefan Roese 提交于
Remove the incorrect PEX macros from the DDR header. And insert the correct ones in ctrl_pex.h instead. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With the upcoming addition of the Armada 38x DDR support, which is not compatible to the Armada XP DDR init code, we need to introduce a new directory infrastructure. To support multiple Marvell DDR controller. This will be the new structure: drivers/ddr/marvell/axp Supporting Armada XP (AXP) devices (and perhaps Armada 370) drivers/ddr/marvell/a38x Supporting Armada 38x devices (and perhaps Armada 39x) Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Pin muxing needs to be done before UART output, since on A38x the UART pins need some re-muxing for output to work. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
On A38x switching the regs base address without running from SDRAM doesn't seem to work. So let the SPL still use the default base address and switch to the new address in the mail u-boot later. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Without calling timer_init(), the xdelay() functions return immediately. We need to call timer_init() early, so that these functions work and the PHY and DDR init code works correctly. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Anton Schubert 提交于
This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Signed-off-by: NAnton Schubert <anton.schubert@gmx.de> Tested-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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- 22 7月, 2015 3 次提交
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由 Simon Glass 提交于
Since we want clk_ops to be used in U-Boot as a whole, rename the Zynq version until it can be converted to driver model. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Driver-model I2C drivers can be picked up by the linker script rule for legacy drivers. Change the order to avoid this. We could make the legacy code depend on !CONFIG_DM_I2C but that is not necessary and it is good to keep conditions to a minimum. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The SPL device tree size must be minimised to save memory. Only include properties that are needed by SPL - this is determined by the presence of the "u-boot,dm-pre-reloc" property. Also remove a predefined list of unused properties from the nodes that remain. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 21 7月, 2015 18 次提交
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由 Zhichun Hua 提交于
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Zhichun Hua 提交于
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: NZhichun Hua <zhichun.hua@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Add dts source files for LS2085AQDS and LS2085ARDB boards. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Add DSPI controller dts node in fsl-ls2085a.dtsi Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Haikun Wang 提交于
Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: NHaikun Wang <Haikun.Wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Acked-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wang Dongsheng 提交于
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Bhupesh Sharma 提交于
This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
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由 Prabhakar Kushwaha 提交于
call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 10 7月, 2015 2 次提交
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由 Stefan Roese 提交于
This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NMarek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Stefan Roese 提交于
This patch adds support for the common AHCI controller on the Marvell Armada 38x. Tested on the Marvell DB-88F6820-GP eval board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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