After a test has failed, test/py drains the U-Boot console log to ensure
that any relevant output is captured. At this point, we don't care about
detecting any additional errors, since the test is already known to have
failed, and U-Boot will be restarted. To ensure that the test cleanup code
is not interrupted, and can correctly terminate the log sections for the
failed test, ignore any exception that occurs while reading the U-Boot
console output during this limited period of time.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Rockchip-focused changes for v2018.11-rc2:
 - fixes to rkimage for SPL boot via USB
 - fixes to make_fit_atf.py, incl. entry-point calculation and python3
   compatibility
 - OP-TEE support for ARMv7-based SoCs
 - fixes to RGMII/GMII selection on the RK3328
Signed-off-by: NTom Rini <trini@konsulko.com>

Here we do a couple of impovements for all ARC boards
as well as introduce yet another developemnt board.

1. Now for ARC boards we print CPU and board info
   which is useful for users and helps with
   analysis of logs "post-mortem".

2. Synopsys IoT development kit support is added
   This one might bw a bit too late as we're past RC1
   but:
    1) This doesn't affect any other arches etc
       as we change purely ARC code.
    2) I've got a chance to talk about U-Boot on
       IoT platforms during ELCE (my proposal was on
       a wait list and only this week I've got
       an update and invitation to talk) so it would
       be good to have this board as a primer in upstream
       code-base by the time of ELCE 2018.
    3) For complete support of IoT devkit I'm yet to
       significantly rework regmap subsystem in U-Boot
       but that's a different topic and hopefully it will
       be done sometime soon... though not this release
       cycle for sure.

The DesignWare ARC IoT Development Kit is a versatile platform
that includes the necessary hardware and software to accelerate
software development and debugging of sensor fusion,
voice recognition and face detection designs.

More information is avaialble here [1] and here [2].

The board is based on real silicon with
ARC EM9D-based Data Fusion IP Subsystem.

It sports a rich set of I/O including
 * DW USB OTG
 * DW MobileStorage (used for micro SD-card)
 * GPIO
 * multiple serial interface including DW APB UART
 * ADC, PWM and eFlash, SRAM and SPI Flash memory
 * Real-Time Clock (RTC)
 * Bluetooth module with worldwide regulatory compliance
   (FCC, IC, CE, ETSI, TELEC)
 * On-board 9-axis sensor (gyro, accelerometer and compass)

Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18
extension header.

One of the most interesting features for developers is built-in
Digilent USB JTAG probe so only micro-USB cable is needed!

[1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit
[2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdfSigned-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

With implemented print_cpuinfo() and model property in .dts
we're ready to print nice info about ARC cores and boards on boot.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Once we enable DISPLAY_CPUINFO for ARC we'll see
ARC core family and version printed on boot.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

1. This way we sync with Linux kernel where we have model
   set for all ARC boards for quite some time, see [1]

2. Once we enable DISPLAY_BOARDINFO for ARC this info will
   be printed on boot givin some extra data-point about the board

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=618a9cd06dd471ac232f5b27325b24d26eba5571Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Even though arc-linux- prefix is used in ARC prebuilt tools and
in Buildroot there're other options like Linux distro cross-tools
etc where prefix is different so let's not rely on this default.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

The 'rkimage' format used for booting rockchip boards over USB seems to
have been broken since commit 7bf274b9 ("rockchip: mkimage: use
imagename to select spl hdr & spl size"). That commit adds an offset of
RK_SPL_HDR_START(=2048) to the location the 'RKxx' header is written
at. However the bootrom expects this header to be the first four bytes of
the image, not at offset 2048. This appears to have been a copy paste
error since the 'rksd' and 'rkspi' image types do require this offset.

Furthermore commit 111bcc4f ("rockchip: mkimage: pad the header to
8-bytes (using a 'nop') for RK3399"), commit 3d54eabc ("rockchip:
spl: RK3399: use boot0 hook to create space for SPL magic") and
commit 30827756 ("rockchip: mkimage: update rkimage to support
pre-padded payloads") changed the way the space for the 'RKxx' header is
allocated and written to the image without adjusting 'rkimage'.

This commit fixes those mistakes and makes it possible to load u-boot SPL
over USB once more.

(Tested on RK3399)
Signed-off-by: NDaniel Gröber <daniel@dps.uibk.ac.at>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

u-boot.itb depends on u-boot-nodtb.bin, which in turn depends on u-boot.
u-boot.its from Rockchip make_fit_atf.py (used by {evb,firefly}-rk3399)
wants to read u-boot but is lacking this dependency, so that u-boot.itb
cannot be built in one go. Detect its use and add the missing dependency.
Reported-by: NYousaf Kaukab <yousaf.kaukab@suse.com>
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.

Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.

Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
Signed-off-by: NJanine Hagemann <j.hagemann@phytec.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
to enable the RX delay.
The MASK was used in a wrong way.
Signed-off-by: NJanine Hagemann <j.hagemann@phytec.de>
Reviewed-by: NPhilipp Tomisch <philipp.tomisch@theobroma-systems.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Make script python3 compatible. No functional changes intended.
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

make_fit_atf.py uses physical address of first segment as the
entry point to bl31. It is incorrect and causes following abort
when bl31_entry() is called:

U-Boot SPL board initTrying to boot from MMC1
"Synchronous Abort" handler, esr 0x02000000
elr: 0000000000000000 lr : 00000000ff8c7e8c
x 0: 00000000ff8e0000 x 1: 0000000000000000
x 2: 0000000000000000 x 3: 00000000ff8e0180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000030 x 7: 00000000ff8e0188
x 8: 00000000000001e0 x 9: 0000000000000000
x10: 000000000007fcdc x11: 00000000002881b8
x12: 00000000000001a2 x13: 0000000000000198
x14: 000000000007fdcc x15: 00000000002881b8
x16: 00000000003c0724 x17: 00000000003c0718
x18: 000000000007fe80 x19: 00000000ff8e0000
x20: 0000000000200000 x21: 00000000ff8e0000
x22: 0000000000000000 x23: 000000000007fe30
x24: 00000000ff8d1c3c x25: 00000000ff8d5000
x26: 00000000deadbeef x27: 00000000000004a0
x28: 000000000000009c x29: 000000000007fd90

Fix it by using the entry point from the elf header.
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

We package U-Boot and OP-TEE into one itb file for SPL,
so that we can support OP-TEE in SPL.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

OP-TEE is an open source trusted OS, in armv7, its loading and
running are like this:
loading:
- SPL load both OP-TEE and U-Boot
running:
- SPL run into OP-TEE in secure mode;
- OP-TEE run into U-Boot in non-secure mode;

To make code simple, it would be fine to use IH_OS_TEE for the
os tyle in TPL(just like IH_OS_LINUX is using both in SPL and U-Boot).

Here is the diagram for SPL loading OP-TEE,
IH_OS_TEE:(make u-boot.itb for SPL)
    Non-Secure       Secure

                     BootROM
                       |
                       v
                      SPL
                       |
                       v
          ---------  OP-TEE
         |
         v
       U-Boot
         |
         V
       Linux
For other two king of OP-TEE loading/booting, see commit message:
45b55712 image: Add IH_OS_TEE for TEE chain-load boot

More detail:
https://github.com/OP-TEE/optee_os
and search for 'boot arguments' for detail entry parameter in:
core/arch/arm/kernel/generic_entry_a32.S
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Patch fix warning:
/builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \
arch/arm/dts/rk3399-firefly.dtb > u-boot.its
  ./tools/mkimage  -f u-boot.its -E u-boot.itb >/dev/null  && cat
/dev/null
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node
/configurations/config@1 has a unit name, but no reg property
make[1]: Leaving directory
'/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399'
Reported-by: NPeter Robinson <pbrobinson@gmail.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.

Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Piotr Dymacz <pepe2k@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Acked-by: NJagan Teki <jagan@openedev.com>

This patch adds support for 2 new XMC (Wuhan Xinxin Semiconductor
Manufacturing Corp) SPI NOR chips.

This support can be enabled by selecting the SPI_FLASH_XMC Kconfig
option.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Rockchip changes for 2018.11

- QEMU support

Add support for the Arm's Versatile Express I2C controller.

Additional sgmii phymode is added in socfpga_phymode_setup() along with
a minor fix for maximum number of GMACs.
Signed-off-by: NOoi, Joyce <joyce.ooi@intel.com>

Remove code from the reset manager that is never called.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Fix sfp_verify_header to return correct version number.
This fixes "Not a sane SOCFPGA preloader" error message with v1 header.
Signed-off-by: NAtsushi Nemoto <atsushi.nemoto@sord.co.jp>

Change to use managed resource function devm_kcalloc(),
so it will auto free memory when driver is removed.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Enable PHY framework on Gen3, this is required for USB EHCI PHY support.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Add a PHY driver for the R-Car Gen3 which allows configuring
USB OTG PHY on Gen3 into host mode and toggles VBUS in case a
dedicated regulator is present.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Mark area 0x1_0000_0000 - 0x10_0000_0000 as DRAM on Gen3 as the
chip is capable of addressing that and U-Boot can make use of it.
This patch prevents exception when accessing those areas.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

The CPfi/4 is derived from XTAL clock and is not fixed. Undo
the previous commit 7984ac8d1635aebd11175c96b07f937a39f0384d.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>

The I2C6 is used to communicate with the PMIC and it was removed
during DT sync with Linux 4.17. Reinstate it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

If environment variable CROSS_COMPILE is not set, this indicates native
compilation. In this case we should not set an arbitrary value which is
not applicable for 64bit anyway.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

The Sentence "reset unsupported yet" is not
grammatically correct and should say
"reset not supported yet" instead.
Suggested-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: NRick Chen <rick@andestech.com>

We don't have a reset method on any RISC-V board yet. Instead of
adding the same 'unsupported' message for each CPU variant it might
make more sense to add a generic do_reset function for all CPU
variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).
Suggested-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

This implies DM support for some common drivers that are used on
RISC-V.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>