There are two issues:

 (1) The spin table doesn't convert the endianness of the jump address.
     Although there is code for it, the result isn't used at all (x0).
 (2) If something goes wrong, the function returns. But that doesn't
     make sense at all.

Use the actual converted jump address as destination to fix. If
there is an error, jump to a trap loop. And rearrange the code exception
level switching code to make it smaller and clearer.

This reduces the size of the spin table code section from 696 bytes to
424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696
bytes to 632 bytes.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate a
new page from EFI, copy the spin table code into it, update any pointers
to the old region and the start the secondary CPUs.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Now that the spin table is in a separate module, this is no longer
necessary. Drop it.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

This function is not used outside the module. Make it static.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

There is no need to cast around. Assign the address to the local
variable and use it.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Only the PowerPC architecture needs this function. Remove it.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.

This saves about 720 bytes in the SPL.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: NMichael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Make the print of the starting address a debug output and pretty print
the info about online cores.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Spin tables are broken with bootefi. This is because - in contrast to
the booti call chain - there is no call to smp_kick_all_cpus(). Due to
this missing call the secondary CPUs are never released from their "wait
for interrupt state", see secondary_boot_func() in lowlevel.S.

Originally, this "wait for interrupt" is there to make sure, the spin
table is cleared before the secondary cores read it for the first time.
But the boot flow for the layerscape architecture is different from
that. The CPUs are release from their BootROM _after_ U-Boot's
spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c.
Thus, there is no need to wait for this interrupt and no need for
kicking all cores on cpu_release. An atomic 64bit write to the
spin-table and a "sev" is sufficient.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Current PFE firmware access spi-nor memory directly. New spi-mem
framework does not support direct memory access. So, let's use
spi_flash_read API to access memory instead of directly using it.
Signed-off-by: NKuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Enable the gpio feature on fsl-layerscape platform.
Signed-off-by: Nhui.song <hui.song_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

add one struct mpc8xxx_gpio_plat to enable gpio feature.
Signed-off-by: Nhui.song <hui.song_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

LS1088A-RDB has MMC, SCSI, DHCP as boot targets,
but the USB support was missing.
Add support for USB as Boot_targets_devices.
Signed-off-by: NEra Tiwari <era.tiwari@nxp.com>
Signed-off-by: NPramod Kumar <pramod.kumar_1@nxp.com>
[Rebased]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to
define it per board; the ls1028a_common.h is really board dependent and
only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE
when ARCH_LS1028A is selected.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.

These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c
Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
        - Don't assume default value for offset and mask property.
        - Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.

This reverts commit 5d3a21df, reversing
changes made to 56d37f1c.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649Signed-off-by: NTom Rini <trini@konsulko.com>

At present the SiFive FU540 RAM driver uses hard-coded memory base
address and size to initialize the DDR controller. This may not be
true when this driver is used on another board based on FU540.

Update the driver to read the memory information from DT and use
that during the initialization.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NLeo Liang <ycliang@andestech.com>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

Make memory node available to SPL in prepration to updates to SiFive
DDR RAM driver to read memory information from DT.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

Use fdtdec_get_addr_size_auto_noparent to read the "reg" property
instead of fdtdec_get_addr. This will increase the compatibility
of dtb parsing.
Signed-off-by: NRick Chen <rick@andestech.com>
Acked-by: NLeo Liang <ycliang@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NLeo Liang <ycliang@andestech.com>

Switch off SMP support when building u-boot-spl would cause linking error as follow:
undefined reference to 'secondary hart relocate' and 'smp_call_function'.
Add macro to wrap up proper code region that needs SMP configuration on.

Signed-off by: Leo Liang <ycliang@andestech.com>
Cc: rick@andestech.com
Reviewed-by: NBin Meng <bin.meng@windriver.com>

The commit 4cc24aea ("serial: Add missing Kconfig dependencies for
debug consoles") has added incorrect dependency for SIFIVE debug uart which
should depend on SIFIVE driver instead of PL01x.

Fixes: 4cc24aea ("serial: Add missing Kconfig dependencies for debug consoles")
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NLeo Liang <ycliang@andestech.com>
Reviewed-by: NSean Anderson <seanga2@gmail.com>

This adds syscon reboot and poweroff support to QEMU RISC-V.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

Per the DT binding, <mask> and <value> property can have either one
or both, and if <value> is missing, <mask> should be used, which is
what current U-Boot sysreset_syscon driver supports.

This adds support to the <value> property to the driver, and <mask>
semantics is updated to really be a mask to the value if both exist.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

Per the DT binding, <offset> is a required property. Let's abort
the probe if it is missing. For the <mask> property, current codes
assume a default value of zero, which is not correct either.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPragnesh Patel <pragnesh.patel@sifive.com>

This reverts commit 23da3c68.

Now the build failure of sifive_fu540_defconfig board has been fixed,
revert this "revert patch".
Signed-off-by: NBin Meng <bin.meng@windriver.com>

This reverts commit 958a3f46.

A more appropriate change below is already in mainline.
Commit fd31e4fd ("riscv: Do not build reset.c if SYSRESET is on")

Revert this patch, so that U-Boot can be built successfully for
SiFive Fu540 board.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NSean Anderson <seanga2@gmail.com>
Reviewed-by: NLeo Liang <ycliang@andestech.com>

Change to use OpenSBI release v0.8 generic platform images for QEMU
RISC-V CI testing for azure, gitlab and travis-ci.
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Enable SPI flash(SF) distro boot command in Sifive FU540.

This distro boot will read the boot script at specific
location at the flash and start sourcing the same.

Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

HiFive-Unleashed-A00 has SPI flash with 32MiB size.
So, let's use the script offset at the end of 4K.
This way it cannot overlap any offsets being used
by software components in flash layout.

So, SF distrocmd will pick the script at desired
script address and run.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

Mark the default U-Boot environment as SPI flash since
this is an on board flash device.
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

SPI flash device on HiFive Unleashed has 32MiB Size.

This patch adds SPI flash environment after U-Boot proper
partition with a size of 128KiB.

SPI flash partition layout(32MiB):
    0 - 34	: reserved for GPT header
   35 - 39	: unused
   40 - 2087	: loader1 (SPL, FSBL)
 2088 - 10279	: loader2 (U-Boot proper, U-Boot)
10280 - 10535	: environment
10536 - 65494	: rootfs
65528 - 65536	: distro script

Note: the loader1 must start from 40th sector even though
there are 6 free sectors prior since 40th sector is nearest
flash sector boundary. 
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Add booting from SPI for SiFive Unleashed board.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Add support to detect boot mode at runtime for
SiFive FU540 boards.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

This patch enables SiFive PWM driver for the SiFive
Unleashed board.
Signed-off-by: NPragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

Commit 40686c39 ("riscv: Clean up IPI initialization code")
caused U-Boot failed to boot on SiFive HiFive Unleashed board.

The codes inside arch_cpu_init_dm() may call U-Boot timer APIs
before the call to riscv_init_ipi(). At that time the timer register
base (e.g.: the SiFive CLINT device in this case) is unknown yet.

It might be the name riscv_init_ipi() that misleads people to only
consider it is related to IPI, but in fact the timer capability is
provided by the same SiFive CLINT device that provides the IPI.
Timer capability is needed for both UP and SMP.

Considering that the original refactor does have benefits, that it
makes the IPI code more similar to U-Boot initialization idioms.
It also removes some quite ugly macros. Let's do the minimal revert
instead of a complete revert, plus a fixes to arch_cpu_init_dm() to
consider the SPL case.

Fixes: 40686c39 ("riscv: Clean up IPI initialization code")
Signed-off-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NSean Anderson <seanga2@gmail.com>
Tested-by: NLeo Liang <ycliang@andestech.com>