The VDDMEM ramped up in very weird way as it was horribly misconfigured.
Instead of setting up VDDMEM in one swipe, let it rise slowly the same
way as VDDD and VDDA in spl_power_init.c and then only clear ILIMIT before
memory gets inited. This makes sure the VDDMEM rises sanely, not jumps up
and down as it did till now.

The VDDMEM prior to this change did this:
     2V0____   .--------2V5
       |    `--'
 0V____|

The VDDMEM now does this:
    2V0_____,-----------2V5
      /
 0V__|

Moreover, VDDIO on MX23 uses 25mV steps while MX28 uses 50mV steps,
fix this difference too.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>

Put an explanation in the source code as to why some DDR registers do not
need to be configured.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

mx23 SSP pad registers do not contain voltage selection bit, so just remove it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

mx23 SSP pad registers do not contain voltage selection bit, so just remove it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

After the recent fixes in the mx23 DDR setup, it is safe to operate DDR voltage
at the recommended 2.5V voltage level again.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: NMarek Vasut <marex@denx.de>

There is no change of behavior, except for the folloing line that has been
removed because the iomux mode was not set accordingly and the pad used for OTG
OC is not this one:
	mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1);
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX53. The content of the file is taken from Freescale's Linux kernel at
commit 4ab3715, plus the required changes to make it work in U-Boot.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior, except for older silicon revisions for which
support is removed.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior, except for older silicon revisions for which
support is removed.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: NMatt Sealey <matt@genesi-usa.com>

There is no change of behavior, except for older silicon revisions for which
support is removed.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Add missing definitions that are required by future changes.

By the way, make some cosmetic cleanup.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

In ALT1 mode, EIM_CS2 is GPIO2[27], not ESDHC1.CD. Hence, rename
MX51_PAD_EIM_CS2__SD1_CD to MX51_PAD_EIM_CS2__GPIO2_27.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

The signal connected from this pin to the PMIC is WDOG_B, i.e. ALT0 mode, not
ALT1 (which even corresponds to nothing).
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX35. The content of the file is taken from Linux kernel at commit
267dd34, plus the required changes to make it work in U-Boot.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior, even if some pad control values could probably
be simplified.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior, even if some pad control values could probably
be simplified.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

There is no change of behavior, even if some pad control values could probably
be simplified.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX25. The content of the file is taken from Linux kernel at commit
267dd34, plus the required changes to make it work in U-Boot.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

Add basic support for the DENX M53EVK board. Currently supported is:
MMC (incl. booting)
NAND (incl. booting)
Ethernet, I2C, USB, SATA, RTC.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>

Augment the MX5 clock code with function to enable and configure
NFC clock. This is necessary to get NFC working on MX5.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>

Fix minor adjustments needed to get SPL framework building on MX5.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>

The U-Boot SPL can parse the uImage format and gather information from
it about the payload. Make use of this and wrap u-boot.bin into uImage
format. The benefit is the SPL will know the size of the payload
instead of using fixed size of the payload defined at compile time.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>

Add support for generic NAND SPL via the SPL framework into the
mxc_nand_spl driver. This is basically just a simple rename and
publication of the already implemented functions. To avoid the
bare-bones functions getting in the way of the NAND_SPL, build
them only if CONFIG_SPL_FRAMEWORK is not defined.

Also make sure the requested payload is aligned to full pages,
otherwise this simple driver fails to load the last page.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: NScott Wood <scottwood@freescale.com>

The MX53 ROM loads the data from NAND in multiples of pages and
supports maximum page size of 4k. Thus, align the image and header
to 4k to be safe from ROM bugs.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>

FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
as 0x2, which means:

PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per
FSL bootlets code.

mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved".

HW_DRAM_CTL8 is setup as the last element.

So skip the initialization of these DRAM_CTL registers.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.

Remove this erroneous setting.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Start bit is part of HW_DRAM_CTL8 register, so  fix the comment.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>