The mainline linux kernel is moving to flatten device tree support
Add the CONFIG_OF_LIBFDT option to support booting DT linux kernel
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Using common spi flash operation function to replace private operation
funtion
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Add atmel at25df321 serial flash support
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Before the patch, it looks like:
	|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06)
	|
	|CPU: AT91SAM9G35
	|Crystal frequency:       12 MHz
	|CPU clock        :      400 MHz
	|Master clock     :  133.333 MHz
	|DRAM:  128 MiB
	|WARNING: Caches not enabled
>	|NAND:  Initialize PMECC params, cap: 2, sector: 512
>	|256 MiB
	|MMC:   mci: 0
	|In:    serial
	|Out:   serial
	|Err:   serial
	|Net:   macb0
	|Hit any key to stop autoboot:  0

After the patch:
	|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11)
	|
	|CPU: AT91SAM9G35
	|Crystal frequency:       12 MHz
	|CPU clock        :      400 MHz
	|Master clock     :  133.333 MHz
	|DRAM:  128 MiB
	|WARNING: Caches not enabled
>	|NAND:  256 MiB
	|	... ...
	|Hit any key to stop autoboot:  0
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch configure at91sam9x5's EBI drive I/O. Without this, When SD card boot, the nand flash read/write are not stable. Which will cause kernel MTD test fail (Since mainline kernel doesn't configure the EBI register).
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that
has been configuring and enabling the timer, so remove our code that
does the same thing by different methods.

Tested on EVM GP, SK-EVM and Beaglebone.
Signed-off-by: NTom Rini <trini@ti.com>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Add a common macros to set the registers for horizontal
and vertical timing.
Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Fix some issues (some pins were not set as GPIOs)
Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NStefano Babic <sbabic@denx.de>

The manufacturer delivers the TAM3517 SOM with 4 MAC address.
They are stored on the EEPROM of the SOM. The patch adds a
function to get their values and set the ethaddr variables.
Signed-off-by: NStefano Babic <sbabic@denx.de>

AM/DM37x SoCs add the CTRL_WKUP_CTRL register.  It contains the
GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads
of gpio_126, gpio_127 and gpio_129.
Signed-off-by: NArnout Vandecappelle (Essensium/Mind) <arnout@mind.be>
Cc: Tom Rini <trini@ti.com>

In order to use the serial interface on the PortuxG20 we need to enable the
level converter first by setting the PC9 pin to high. The level converter needs
some time to settle so we have to use the mdelay() function to wait for some
time. Unfortunately we have no timers available at board_early_init_f() so we
enable the serial output early within board_postclk_init().

Now the U-Boot output looks fine:

| U-Boot 2012.07-00132-gaf1a3b0-dirty (Aug 16 2012 - 18:21:32)
|
| CPU: AT91SAM9G20
| Crystal frequency:   18.432 MHz
| CPU clock        :  396.288 MHz
| Master clock     :  132.096 MHz
| DRAM:  64 MiB
| WARNING: Caches not enabled
| NAND:  128 MiB
| In:    serial
| Out:   serial
| Err:   serial
| Net:   macb0
| Hit any key to stop autoboot:  0
Signed-off-by: NMarkus Hubig <mhubig@imko.de>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The board_postclk_init() function can be used to perform operations
that requires a working timer early within the U-Boot init_sequence.
Signed-off-by: NMarkus Hubig <mhubig@imko.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

* add ram target for EB+CPUx9k2 board (eb_cpux9k2_ram_config)
Signed-off-by: NJens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The configuration that is common for all Integrator boards may
just as well be stored in a common include file as per pattern
from other boards. This eases maintenance quite a bit.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

* fix chip select initialization for frame buffer, this will be
  increase frame buffer access speed
Signed-off-by: NJens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch restores the Linkstation's original behaviour when powering off.
Once the (soft) power switch is turned off, linux will reboot and the
bootloader turns off HDD and USB power. Then it loops as long as the switch
is in the off position, before continuing the boot process again.

Additionally, this patch fixes the board function set_led(LED_OFF).
Signed-off-by: NMichael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>

Hi,

This adds to the documenation to explain how to use the
kwbimage.cfg file necessary to generate an image with
prefixed board setup values necessary for the kirkwood
boards.
Signed-off-by: NKarl O. Pinc <kop@meme.com>

Signed-off-by: NKarl O. Pinc <kop@meme.com>

For some reasons we had an own implementaion of dram_init and
dram_init_banksize. This is not needed anymore, use the standard
kirkwood functions instead.
Signed-off-by: NHolger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Acked-By: NPrafulla Wadaskar <prafulla@marvell.com>

According to our last HW measures, this could be raised while still
compatible with the potential delays on the lines.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
Acked-By: NPrafulla Wadaskar <prafulla@marvell.com>

The fanless boards now have a 7-digit (XXXXX-F) board name. This
triggers a border condition when reading this string in the IVM although
this string is smaller than the currenly read string size, but only by 1
character.

This patch corrects this by changing the size check condition for string
length. It is the same change that was done in the platform for this
same bug.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Stefan Bigler <stefan.bigler@keymile.com>

The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.

This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: NPrafulla Wadaskar <Prafulla@marvell.com>
Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>

These parameters are used by the the sf probe command that are used by
our update script and they therefore need to be set for all of our
boards.

The timing is the same as for the ENV SPI NOR Flash (since it's the
same physical device) and takes the boco2 delay on the bus into account.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: NPrafulla Wadaskar <Prafulla@marvell.com>

Orion5x did not actually write GPIO output values
or input polarities, and ED Mini V2 had bad or
missing values for GPIO settings.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Acked-By: NPrafulla Wadaskar <prafulla@marvell.com>

* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
  tx25: Use generic gpio_* calls
  config: Always use GNU ld
  tools: add kwboot binary to .gitignore file
  fdt: Include arch specific gpio.h instead of asm-generic/gpio.h
  serial: CONSOLE macro is not used

Conflicts:
	board/karo/tx25/tx25.c
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Tested-by: voice.shen@atmel.com
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The Programmable Multibit ECC (PMECC) controller is a programmable binary
BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
can be used to support both SLC and MLC NAND Flash devices. It supports to
generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data.

To use PMECC in this driver, the user needs to set the PMECC correction
capability, the sector size and ROM lookup table offsets in board config file.

This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference
is in this version it uses registers structure access hardware instead of using macros.
It is tested in 9x5 serial boards.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
[rebase]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch
1. extract the hwecc initialization code into one function. It is a preparation for adding atmel PMECC support.
2. enable CONFIG_SYS_NAND_SELF_INIT. Which make us can configurate the ecc parameters between nand_scan_ident() and nand_scan_tail().
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
[fix empty newline at EOF error and move return value check into ifdef]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Add at91sam9x5 series spi flash boot support

Using at91sam9x5ek_spiflash to configure, then it can boot from at25df321
serial flash

SPI mater work in 30Mhz speed, while not 1Mhz speed. This will base on
atmel_spi patch, or else, it will occur receive overrun
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Remove CONFIG_ARCH_CPU_INIT for at91sam9g10ek and at91sam9m10g45ek
Signed-off-by: NBo Shen <voice.shen@atmel.com>
[rebase on TOT]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>