- 27 6月, 2017 1 次提交
-
-
由 Bin Meng 提交于
This reverts commit ddb3ac3c. With MMC converted to driver model, SCSI driver is broken due to zero address access at (ops->read) in block_dread() function. The fix (SCSI driver converted to DM) is ready in u-boot-dm branch, but it is too late for this relese to get that in. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
- 23 6月, 2017 24 次提交
-
-
-
由 Kever Yang 提交于
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
-
由 Kever Yang 提交于
The maximum spl_size for rk3399 is the internal memory size minus the size used in bootrom (which usually can get from SPL_TEXT_BASE). Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
-
由 Kever Yang 提交于
The SPL_MAX_SIZE is the internal memory size minux the space used by bootrom. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
-
由 Tom Rini 提交于
This function is unused, remove. Reported by clang-3.8. Fixes: a1c29d4b ("rockchip: mkimage: set init_boot_size to avoid ...") Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
-
由 Heiko Schocher 提交于
since commit: f8b7fff1 "serial: atmel_usart: Add clk support" corvus board comes not up anymore. Fix it. Signed-off-by: NHeiko Schocher <hs@denx.de>
-
由 Philipp Tomsich 提交于
Adding myself to MAINTAINERS and git-mailrc for the rockchip sub-architecture. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
-
由 Heiko Schocher 提交于
fix menutext for the options SPL_DM_SERIAL and TPL_DM_SERIAL. Both have the same text as DM_SERIAL, which is confusing. Signed-off-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NStefan Roese <sr@denx.de>
-
由 Heiko Schocher 提交于
for debugging it is handy to know the fdt_blob address. So print it in bdinfo. Signed-off-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
-
由 Rob Clark 提交于
Otherwise the loaded image would miss the efi_runtime sections, and fall over hard when grub (for example) tried to call runtime services located in this section. Signed-off-by: NRob Clark <robdclark@gmail.com>
-
由 Ladislav Michl 提交于
commit dfe64e2c Author: Sergey Lapin <slapin@ossfans.org> Date: Mon Jan 14 03:46:50 2013 +0000 mtd: resync with Linux-3.7.1 modified onenand_block_markbad to call mtd_block_markbad, but as _block_markbad function pointer used by mtd_block_markbad to do actual job is by default pointing back to onenand_block_markbad there is no way this function ever finishes its job. Fix it by changing function body according current (4.12-rc6) linux implementation. Tested on IGEPv2 board with Muxed OneNAND(DDP) 512MB containing several unerasable blocks this function marked bad. Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
-
由 Ladislav Michl 提交于
Current implementation is unable to access second half of DDP OneNAND flash (reads first half mirrored). Use block and bufferram address calculations from onenand_base to fix this. Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
-
由 Ladislav Michl 提交于
Do not call onenand_spl_get_geometry() for each block read. Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
-
由 Emmanuel Vadot 提交于
Define a default number of 1 for mmc max device if board config didn't specify one. Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Tom Rini 提交于
The variables gpll_init_cfg and apll_init_cfg are unused in this file, remove them. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Tom Rini 提交于
The variable syndrome_codes is only used when DEBUG is define, add #if guards around it in the same style as the rest of the file. Cc: Stefan Roese <sr@denx.de> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NStefan Roese <sr@denx.de>
-
由 Tom Rini 提交于
On the controlcenterd_36BIT_SDCARD config we get a warning about prg_stage1_prepare being unused. Move the declaration closer to usage and hide under the existing #if tests. Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Lokesh Vutla 提交于
Now that we can specify DT nodes that can be used in spl, mark all necessary nodes as u-boot,dm-spl. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
-
由 Lokesh Vutla 提交于
Now that we can specify DT nodes that can be used in spl, mark all necessary nodes as u-boot,dm-spl. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
-
由 Tom Rini 提交于
It has been observed that between PG1.0 and PG2.0/2.1 depending on which device we boot from, we may see a different value here than is documented in the TRM. Update the values for NAND and MMC1 based on real life usage on each revision. Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Semen Protsenko 提交于
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org> Reviewed-by: NTom Rini <trini@konsulko.com>
-
-
由 Ken Ma 提交于
In armada_37xx_gpiochip_register, the return value of fdtdec_get_bool should be true when gpio-controller is found; current codes makes a wrong inverse return value judgement, this patch fixes it. Signed-off-by: NKen Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Ken Ma 提交于
If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: NKen Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
- 22 6月, 2017 2 次提交
-
-
由 Bin Meng 提交于
As all x86 boards have been switched over to use DM USB, remove CONFIG_USB_MAX_CONTROLLER_COUNT which is not used by DM USB. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NStefan Roese <sr@denx.de> Tested-by: NStefan Roese <sr@denx.de>
-
由 Bin Meng 提交于
GPIO bank E pin 8 & 9 are used to control the on-board two USB ports VBUS on/off. Let's configure them in the misc_init_r(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NStefan Roese <sr@denx.de> Tested-by: NStefan Roese <sr@denx.de>
-
- 21 6月, 2017 9 次提交
-
-
-
-
git://www.denx.de/git/u-boot-microblaze由 Tom Rini 提交于
Xilinx changes for v2017.07 ZynqMP: - config cleanup - SD LS mode support - psu_init* cleanup - unmap OCM - Support for SMC Zynq: - add ddrc to Kconfig - add topic-miamilite board support
-
由 Fabio Estevam 提交于
I would like to help Stefano Babic as a co-maintainer of U-Boot i.MX. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NStefano Babic <sbabic@denx.de> Acked-by: NJagan Teki <jagan@amarulasolutions.com>
-
由 Tom Rini 提交于
On ARCH_SUNXI we've been selecting these targets for a long time if SUPPORT_SPL is set. However, Lichee Pi Zero is the first platform we've added that does support SPL but does not build SPL and has exposed a latent bug. Both of these symbols depend on SPL not SUPPORT_SPL, so we need to update our select here otherwise we get a Kconfig warning. Fixes: f02abb06 ("sunxi: add support for Lichee Pi Zero") Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Marek Vasut 提交于
The commit "fb82fe38 configs: Resync defconfigs" resynced all config files. This exposed two latent issues with the Gen3 boards in that we had not been setting CONFIG_DEFAULT_FDT_FILE correctly and had not been setting CONFIG_CMD_MMC. Fix both of these. Fixes: fb82fe38 ("configs: Resync defconfigs") Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Marek Vasut 提交于
Trivial, fix typo. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
-
由 Emmanuel Vadot 提交于
endian.h on FreeBSD system exist in sys/ subdirectory. FreeBSD already have a fls function defined in strings.h which is included in string.h if __BSD_VISIBLE is defined, as a check for this. Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com>
-
由 Simon Glass 提交于
The driver currently does not reset bit 5 of the hostctl register even if the MMC stack requests it. Then means that once a bus width of 8 is selected it is not possible to change it back to 1. This breaks 'mmc rescan' which needs to start off with a bus width of 1. The problem was surfaced by enabling CONFIG_DM_MMC_OPS on tegra. Without this option the MMC stack fully reinits the driver on a 'mmc rescan'. But with this option driver model does not re-probe a driver once it has been probed once. Fix the driver to honour the request. Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NPeter Chubb <peter.chubb@data61.csiro.au> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
-
- 20 6月, 2017 4 次提交
-
-
由 Mike Looijmans 提交于
The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM, 64MB dual-parallel QSPI NOR flash and clock sources. Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Mike Looijmans 提交于
Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the associated topic_miamiplus.h header obsolete, so remove that as well. Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
由 Michal Simek 提交于
If PMUFW version is not v0.3 then panic. ZynqMP switch to CCF based clock driver which requires PMUFW to be present at certain version. This patch ensure that you use correct and tested PMUFW binary. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-
Reuse invoke_smc() routine which is already defined instead of duplicating same at multiple places. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
-