This driver is used for MDIO muxes driven over I2C.  This is currently
used on Freescale LS1028A QDS board, on which the physical MDIO MUX is
controlled by an on-board FPGA which in turn is configured through I2C.
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Adds a driver for the MDIO interface currently integrated in LS1028A SoC.
This MDIO interface is shared by multiple ethernet interfaces and is
presented as a stand-alone PCI function on the SoC ECAM.
Ethernet has a functional dependency on MDIO, for simplicity there is a
single config option for both.
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Adds a driver for NXP ENETC ethernet controller currently integrated in
LS1028A.  ENETC is a fairly straight-forward BD ring device and interfaces
are presented as PCI EPs on the SoC ECAM.
Signed-off-by: NCatalin Horghidan <catalin.horghidan@nxp.com>
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Adds a test using a makeshift MDIO MUX.  The test is based on the existing
MDIO test.  It uses the last emulated PHY register to verify MUX selection.
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Adds a class for MDIO MUXes, which control access to a series of
downstream child MDIOs.
MDIO MUX drivers are required to implement a select function used to switch
between child buses.
MUX children are registered as MDIO buses and they can be used just like
regular MDIOs.
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices.  Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.
Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Move the main symbol for Freescale Fman Ethernet controller option to
Kconfig.  Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and
rename the SPIFLASH one to follow the same format as all of the others.
To do this fully we need to migrate CONFIG_QC, do so.
Signed-off-by: NTom Rini <trini@konsulko.com>

Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.

Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>

It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200.  It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NLukasz Majewski <lukma@denx.de>
Reviewed-by: NStefan Agner <stefan.agner@toradex.com>

Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.

This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

This driver was written for Arria10, but it applies to Gen5, too.

The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.

This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.

Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.

To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.

Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>

This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

This patch adds ethernet support for Mediatek ARM-based SoCs, including
a minimum setup of the integrated switch.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMark Lee <Mark-MC.Lee@mediatek.com>
Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
Tested-By: N"Frank Wunderlich" <frank-w@public-files.de>

Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add compatible property and enable the FEC ipg clock when probing
on i.MX8X. Add specific function for reading FEC clock rate via
clock driver when configuring MII speed register. Allow FEC_MXC
selection for i.MX8.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This converts the following to Kconfig:
   CONFIG_MII
   CONFIG_DRIVER_TI_EMAC
Signed-off-by: NAdam Ford <aford173@gmail.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>

Add driver model support to the mvgbe driver. As a temporary measure
both DM and non-DM uses are supported. Once all the users have been
converted the non-DM support can be dropped.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Tested-by: NMichael Walle <michael@walle.cc>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add driver for Socionext AVE ethernet controller that includes MAC and
MDIO bus supporting RGMII/RMII modes.
The driver behaves the ethernet driver model (DM_ETH) with devicetree.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

When Kconfig support was added for MVGBE it included automatically
selected PHYLIB support. But MVGBE does not need PHYLIB it will build
fine without it. Commit ed52ea50 ("net: add Kconfig for MVGBE")
should have been a no-op in terms of build size but because of the
selecting PHYLIB the openrd configs increased in size.

Remove the automatic selection of PHYLIB, boards that need it will have
already enabled it in their config header file.

Fixes: commit ed52ea50 ("net: add Kconfig for MVGBE")
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add Kconfig for MVGBE and update boards to select this.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>

On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. But Some boards share one MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.

To i.MX28, adapt to use the new config
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>

This converts CONFIG_DRIVER_TI_CPSW to Kconfig
Signed-off-by: NAlex Kiernan <alex.kiernan@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Migrate the CONFIG_TSEC_ENET option to Kconfig.
Signed-off-by: NMario Six <mario.six@gdsys.cc>

CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.
Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr>

Add configurations for PFE.
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NAnjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This adds SH_ETHER to drivers/net/Kconfig and convert to Kconfig.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Although Xilinx Zynq SoC was using MACB similar hardware. However,
U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is
to add support for the Xilinx Zynq SoC to the existing MACB network
driver.

This patch is to add Zynq GEM DMA Config, provide callback
function for different linkspeed for case of using Xilinx Zynq
Programmable Logic as GMII to RGMII converter.

This patch convert the return value to use error codes.
Signed-off-by: NWilson Lee <wilson.lee@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part
Signed-off-by: NAhmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus
did not benefit from Ethernet support. Add ARMADA_3700 in the
"depends on" list of the MVNETA Kconfig entry.
Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NStefan Roese <sr@denx.de>

>From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.
Signed-off-by: NStefan Mavrodiev <stefan@olimex.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>