This converts the following to Kconfig:
   CONFIG_CMD_EECONFIG
Signed-off-by: NSimon Glass <sjg@chromium.org>

This converts the following to Kconfig:
   CONFIG_CMD_ECCTEST
Signed-off-by: NSimon Glass <sjg@chromium.org>

This is only used by one board and always set to 0x51. Drop this option.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Now that dtt is gone, this is not used. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

This subsystem is quite old. It has been replaced with a driver-model
version (UCLASS_THERMAL). Boards are free to convert to that if required,
but here is a removal patch that could be applied in the meantime.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

This subsystem has not been converted to driver model, there is only one
driver and only one board that uses it. Drop it and its CONFIG option.

Also drop the rtc4543 RTC driver since it uses TWS.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

This option is only defined to a non-default value by canyonlands, which
needs conversion to driver model (where the I2C address would be defined
by the device tree).

Drop this option.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This converts the following to Kconfig:
   CONFIG_DS4510
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This option enables a command in the driver. But the functions defined by
the driver are not called anywhere else in U-Boot. So it does not seem
useful to have this driver without its commands.

Drop this option, move the header file out of the common include/
directory and make all the function static.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This option is only used in one driver and is not enabled by any board. It
does not seem worth having the ability to remove this part of the support.

Drop the option.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This option is only used in one driver and is not enabled by any board. It
does not seem worth having the ability to remove this part of the support.

Drop the option.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This option is only used in one driver and two boards. It does not seem
worth having the ability to remove this part of the support.

Drop the option.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Commit 94e3c8c4 ("crypto/fsl - Add progressive hashing support
using hardware acceleration.") created entries for CONFIG_SHA1,
CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
However, no defconfig has migrated to it.  Complete the move by first
adding additional logic to various Kconfig files to select this when
required and then use the moveconfig tool.  In many cases we can select
these because they are required to implement other drivers.  We also
correct how we include the various hashing algorithms in SPL.

This commit was generated as follows (after Kconfig additions):

[1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
[2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL

Note:
We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
because there is dependency between them.

Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Feng Li <feng.li_2@nxp.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Cc: Mingkai Hu <Mingkai.Hu@freescale.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

We rename CONFIG_FIT_DISABLE_SHA256 to CONFIG_FIT_ENABLE_SHA256_SUPPORT which
is enabled by default and now a positive option.  Convert the handful of boards
that were disabling it before to save space.

Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Lukasz Dalek <luk0104@gmail.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

There is missing dependency on echo command. Mark tests which requires
echo.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

This converts the following to Kconfig:
   CONFIG_SPL_BOARD_INIT
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Signed-off-by: NTom Rini <trini@konsulko.com>

SDIO is not supported in u-boot, there is no point in enabling mmc3.
For this purpose, add u-boot specific dtsi that this will be included
automatically while building the dtb.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

The intention of having a -u-boot.dtsi file is to be able to make
changes to the provided upstream dts files as well as to be able to add
nodes.  Change the logic for adding the file from making it the last
included file at the top of the dts to being included at the end of the
file.

Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>
Tested-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NStefano Babic <sbabic@denx.de>

Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add support for the Arria10 SoCDK.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add config and defconfig for the Arria10 and update socfpga_common.h.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add SPL support for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Device tree files for Arria 10
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add misc support for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add pinmux support for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add sdram header file for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add system manager register struct and macros for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add clock driver support for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add reset driver support for Arria 10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add i2c, timer and other A10 macros.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.

Change all uint32_t_to u32.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Restructure system manager in the preparation to support A10.
No functional change.

Change uint32_t to u32.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add DM support for i2c functions.
Signed-off-by: NLiam Beguin <lbeguin@tycoint.com>
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>
Reviewed-by: NMarek Vasut <marex@denx.de>

Each time set_state is called, a new piece memory will
be allocated for pin_data, but not freed, this will
incur memory leak.

When error, the devm API could not free memory automatically.
So need call devm_kfree when error.

Issue reported by Coverity
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>