- 21 5月, 2014 14 次提交
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由 Nobuhiro Iwamatsu 提交于
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Lager board has USB ports. This add support of USB controller of rmobile. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Koelsch board has USB ports. This add support of USB controller of rmobile. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
This adds CONFIG_SYS_THUMB_BUILD to config, in order to enable optimization of thumb. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Because do not need these feature to lager board, this delete it. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
The define of SCIF register was already defined in rcar-base.h. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
This adds CONFIG_SYS_THUMB_BUILD to config, in order to enable optimization of thumb. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Because do not need these feature to koelsch board, this delete it. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
The define of SCIF register was already defined in rcar-base.h. Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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由 Nobuhiro Iwamatsu 提交于
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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- 20 5月, 2014 2 次提交
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由 Albert ARIBAUD 提交于
Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
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由 Albert ARIBAUD 提交于
Apply command "tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg" in preparation of pull request from ARM to main tree.
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- 17 5月, 2014 17 次提交
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由 Liu Gang 提交于
The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Kim Phillips 提交于
AFAICT, c=ffe does nothing and was a typo from the original commit d1712369 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Acked-by: NEdward Swarthout <ed.swarthout@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
In the earlier patches, the SPL/TPL fraamework was introduced. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
In case of secure boot from NAND, CSPR and FTIM settings are same as non-secure NAND boot. CSPR0 is configured as NAND and CSPR1 is configured as NOR. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 ramneek mehresh 提交于
P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shaveta Leekha 提交于
B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NSandeep Singh <Sandeep@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
T4160RDB shares the same platform as T4240RDB. T4160 is a low power version of T4240, with the eight e6500 cores, two DDR3 controllers, and same peripheral bus interfaces. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tang Yuantian 提交于
T104xrdb has several sleep management signals that are used for deep sleep. They are enabled by OS to enter deep sleep and should be disabled by u-boot when cores wake up. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ebony Zhu 提交于
According to AN3638, CRC of NXID v1 is at the end of the 256-byte I2C memory. The wrong CRC32 offset prevents Uboot from reading system information from EEPROM. No NXID v0 is being used on Freescale boards. Signed-off-by: NEbony Zhu <b45385@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Albert ARIBAUD 提交于
Conflicts: boards.cfg Trivial conflict, maintainer change plus board addition
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由 Simon Glass 提交于
There is an unfortunate bug in the signoff suppression logic. The first pass is performed with 'git log', and all signoffs are added to the supression set, such that the second time (when processing the real patches) we always suppress the signoffs. Correct this by only suppressing signoffs in the second pass. Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NMichal Simek <monstr@monstr.eu> Tested-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Masahiro Yamada 提交于
Because sandbox is not a real hardware, setting vendor=sandbox is almost meaningless. This commit sets sandbox's vendor field to '-'. It is a good thing that it decreases one level directory hierarchy. The files board/sandbox/sandbox/* have been moved to board/sandbox/*. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
This reverts commit 25806090. Conflicts: boards.cfg Wrong patch 25806090 was applied by accident. Revert it. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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- 16 5月, 2014 2 次提交
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由 Albert ARIBAUD 提交于
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由 Albert ARIBAUD 提交于
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- 15 5月, 2014 5 次提交
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由 Albert ARIBAUD 提交于
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由 Albert ARIBAUD 提交于
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由 Albert ARIBAUD 提交于
Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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由 Albert ARIBAUD 提交于
PXA start.S has a PXA (variant) specific check in start.S. Move it to cpuinfo.c. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: NMarek Vasut <marex@denx.de>
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