- 08 2月, 2021 40 次提交
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for board ls1021aqds Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for board ls1021atwr Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable MPC8XXX_GPIO for SoC LS1046A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for SoC LX2160A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for LS208xA Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for LS1088A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for SoC LS1028A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for SoC LS1043A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Enable CONFIG_MPC8XXX_GPIO for SoC LS1012A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS208xA Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS1088A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS1046A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS1043A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS1028A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS1012A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Add gpio node for SoC LS1021A Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Biwen Li 提交于
Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Hou Zhiqiang 提交于
Drop the CONFIG_VIDEO to fix the following build warning. ===================== WARNING ====================== This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. UPD include/generated/dt.h Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. UPD include/generated/timestamp_autogenerated.h ==================================================== Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Priyanka Jain 提交于
Update data type of '1' to '1ull' in below assignment size = 1ull << sizebit; to fix incorrect assignment issue. e.g: when sizebit was 31, 0x80000000 got sign extended to 0xffffffff_80000000 Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reported-by: NDean Saridakis <dean.saridakis@baesystems.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Hou Zhiqiang 提交于
Enable the I-Cache to speed up the boot time, especailly for the NOR boot, currently it takes about 15 seconds from power up to the U-Boot prompt, and with the I-Cache enabled it only takes around 2.5 seconds. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Aleksandar Gerasimovski 提交于
Cleanup, move the declarations to keymile/common.h instead declaring them per-board config.h Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Hou Zhiqiang 提交于
LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NWasim Khan <wasim.khan@nxp.com> Tested-by: NWasim Khan <wasim.khan@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Hou Zhiqiang 提交于
This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NWasim Khan <wasim.khan@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Mathew McBride 提交于
The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: NMathew McBride <matt@traverse.com.au> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Mathew McBride 提交于
Adapted from kernel commit b0177aca7aea From: Michael Walle <michael@walle.cc> Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: NMichael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.ccSigned-off-by: NMark Brown <broonie@kernel.org> Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot] Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Mathew McBride 提交于
spi_mem_default_supports_op is used internally by controller drivers to verify operation semantics are correct. It is used internally inside spi-mem but has not (in U-Boot) been declared in spi-mem.h for external use. Signed-off-by: NMathew McBride <matt@traverse.com.au> Reviewed-by: NPratyush Yadav <p.yadav@ti.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Niel Fourie 提交于
Add basic support for the Hitachi Power Grids kmcent2 board, based on the NXP QorIQ T1040 SoC. Signed-off-by: NValentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Signed-off-by: NRainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: NNiel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: NStefan Roese <sr@denx.de> [Fixed blank line at EOF errors] Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Niel Fourie 提交于
Replace instances of sprintf()/set_env() for setting hexadecimal values with set_env_hex(). In set_km_env() the "pram" variable was set to an hexadecimal value, while initr_mem() expects an unsigned decimal, so use set_env_ulong() instead. Signed-off-by: NNiel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: NStefan Roese <sr@denx.de> [Rebased] Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Niel Fourie 提交于
Pulled in the kmcent2.dts and all its dependents from Linux 5.10, commit 2c85ebc57b3e upstream. Replaced the license text with SPDX License Identifiers. Signed-off-by: NNiel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Aleksandar Gerasimovski 提交于
Take into account SDRAM_BASE address when calculating pnvramaddr and varaddr offsets. Up to now Keymile designs had SDRAM_BASE equal to zero and the offsets where calculated correctly, this fix is for the upcoming designs that have SDRAM_BASE different then zero. Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Aleksandar Gerasimovski 提交于
Add show_qrio function to print chip id and revision information. There are already multiple QRIO chip versions available and the upcoming designs may want to show used version. Signed-off-by: NRainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Aleksandar Gerasimovski 提交于
This patch is fixing qrio driver compilation for ARM architecture: - It includes asm/io.h for in_/out_ access - It use correct names for set/clear_bits as defined in linux/bitops.h Signed-off-by: NAleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Wasim Khan 提交于
Multiple LX2(LX2160A/LX2162A SoC) personality variants exists based on CAN-FD and security bit in SVR. Currenly SVR_SOC_VER mask only security bit. Update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products. Signed-off-by: NWasim Khan <wasim.khan@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Nipun Gupta 提交于
When A-050382 errata is enabled, ECAM and EDMA have conflicting stream id 40. This patch fixes the same. Signed-off-by: NNipun Gupta <nipun.gupta@nxp.com> Reviewed-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Michael Walle 提交于
Enable SATA support. Although not supported by the usual SATA pins on the SMARC baseboard connector, SATA mode is supported on a PCIe lane. This way one can use a mSATA card in a Mini PCI slot. We need to invert the received data because in this mode the polarity of the SerDes lane is swapped. Provide a fixup in board_early_init_f() for the SPL. board_early_init_f() is then not common between SPL and u-boot proper anymore, thus common.c is removed, as it just contained said function. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Michael Walle 提交于
Although this variant has two external network ports, they are not (yet) supported by the bootloader because they are connected via an internal network switch. Otherwise its the same as the other variants. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Michael Walle 提交于
This variant has one network port connected via RGMII and doesn't have any TSN capabilities out-of-the-box. Instead it has all four SerDes lanes available for customer use. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Michael Walle 提交于
The variants differ in their network configuration. Move the first two network aliases to the proper variant device tree includes. This is in prepartion for variant 1 and 2 support which has a different network port mapping. The network aliases for the two internal ports will stay in the common dtsi because they are present on all board variants. This might leave a hole if there is no ethernet1 alias. This is intended. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Ye Li 提交于
Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NFugang Duan <Fugang.duan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Zhao Qiang 提交于
Add dspi node into lx2162aqds device tree Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com> [Rebased] Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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