- 19 9月, 2018 16 次提交
-
-
由 Ofer Heifetz 提交于
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Ofer Heifetz 提交于
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the one that is already part of struct nand_chip. This brings us in line with current U-boot and Linux conventions. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Ofer Heifetz 提交于
The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. This commit is taken from Linux: 'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Marek Behún 提交于
If PCIe Mox module is connected we want to have PCIe node enabled in U-Boot's device tree. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Baruch Siach 提交于
Commit 61dccf73 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added a redundant DT node for SD card slot. Drop it. Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Marek Behún 提交于
Remove smi_pins definition since it is already in armada-37xx.dtsi. Add assigned-clocks definitions to spi0. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Marek Behún 提交于
Enable the pci-aardvark driver in defconfig for Turris Mox and also enable the pci command. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Marek Behún 提交于
The macro name CONFIG_WDT_ARMADA_3720 is called CONFIG_WDT_ARMADA_37XX instead. Fix this so that watchdog really is enabled in board_init. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Marek Behún 提交于
Add support for changing clock rate and parent clock for Armada 37xx peripheral clocks. Only clocks which can be disabled (.can_gate is true) can have parent or rate changed. This is needed so that Turris Mox can change SPI clock in device tree. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Marek Behún 提交于
This adds a weak definition of comphy_update_map to comphy_core, which does nothing. If this function is defined elsewhere, for example in board file, the board file can change some parameters of SERDES configuration. This is needed on Turris Mox, where the SERDES speed on lane 1 has to be set differently when SFP module is connected and when Topaz Switch module is connected. This is a temporary solution. When the comphy driver for armada-3720 will be added to the kernel, the comphy driver in u-boot shall also be updated and this should be done differently then. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Chris Packham 提交于
The bootROM in the Armada-38x (and similar) SoC has two modes for UART boot. The first is when the normal boot media is blank (or otherwise missing the kwb header). The second is when the boot sequence has been interrupted with the magic byte sequence on the UART lines. In the first mode the bootROM routine and error code register will indicate that there was an error booting from the configured media in bits 7:0. In the second mode there is no error to indicate but the boot source is provided via bits 31:28. Handle both situations so that kwboot can be used for both boot strapping a blank board and for intercepting a regular boot sequence. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NSean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Chris Packham 提交于
This reverts commit e83e2b39. This prevents kwboot from overriding the hardware strapped boot source. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Baruch Siach 提交于
Detect the SD/eMMC boot device at run-time. Load the environment from the boot deice, as well as save to it. Leave the environment offset the same as in the SPI flash. Make SD/eMMC 0 the default environment device when the boot device is not detected. Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Jon Nettleton 提交于
This patch accomplishes 2 things to make the kwboot procedure on the a38x more reliable. 1) We fill the tty with 1K of the magic bootparam. This helps with the timing of where the microcode picks up in the read of the line to ensure we actually catch the break to go into recovery mode 2) Before starting the xmodem transfer we sleep for 2 seconds and then flush the line. This allows all the magic bootparam to be flushed from the line and makes the xmodem transfer reliable and removes the Bad message failures. Signed-off-by: NJon Nettleton <jon@solid-run.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Baruch Siach 提交于
Stefan is listed as a kirkwood maintainer since commit f822d857 (MAINTAINERS: Update Marvell custodianship). Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Evgeni Dobrev 提交于
The default bootdelay of 3 seconds is good enough and there is no need to duplicate it in CONFIG_EXTRA_ENV_SETTINGS. Signed-off-by: NEvgeni Dobrev <evgeni@studio-punkt.com> Signed-off-by: NStefan Roese <sr@denx.de>
-
- 17 9月, 2018 7 次提交
-
-
-
由 Georgii Staroselskii 提交于
These comments were copied from the Linux kernel driver in drivers/platform/x86/intel_scu_ipc.c Signed-off-by: NGeorgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Georgii Staroselskii 提交于
Now that we have I2C#6 working, it's time to add a corresponsing ACPI binding. Signed-off-by: NGeorgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Georgii Staroselskii 提交于
Now that we have the pinctrl driver for Merrifield in place we can make use of it and set I2C#6 pins appropriately. Initial configuration came from the firmware. Which quite likely has been used in the phones, where that is not part of Atom peripheral, is in use. Thus we need to override the leftover. Signed-off-by: NGeorgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Georgii Staroselskii 提交于
This API is going to be used to configure some pins that are protected for simple modification. It's not a comprehensive pinctrl driver but can be turned into one when we need this in the future. Now it is planned to be used only in one place. So that's why I decided not to pollute the codebase with a full-blown pinctrl-merrifield nobody will use. This driver reads corresponding fields in DT and configures pins accordingly. The "protected" flag is used to distinguish configuration of SCU-owned pins from the ordinary ones. The code has been adapted from Linux work done by Andy Shevchenko in pinctrl-merrfifield.c Signed-off-by: NGeorgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> [bmeng: fix build warning] Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Georgii Staroselskii 提交于
This interface will be used to configure properly some pins on Merrifield that are shared with SCU. scu_ipc_raw_command() writes SPTR and DPTR registers before sending a command to SCU. This code has been ported from Linux work done by Andy Shevchenko. Signed-off-by: NGeorgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Christian Gmeiner 提交于
This will add support for a baud rate of 57600. Signed-off-by: NChristian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
- 16 9月, 2018 7 次提交
-
-
-
-
-
-
由 Angelo Dureghello 提交于
This patch adds mcf5441x eSDHC support for the mcf5441x family. Signed-off-by: NAngelo Dureghello <angelo@sysam.it>
-
由 Angelo Dureghello 提交于
On a u32 val = __sw32(*addr); multiple memory accesses are not welcome, since "addr" may be an IO peripheral register address. This patch changes __sw16/32 to perform a single memory access for the source value. Signed-off-by: NAngelo Dureghello <angelo@sysam.it>
-
由 Angelo Dureghello 提交于
Signed-off-by: NAngelo Dureghello <angelo@sysam.it>
-
- 15 9月, 2018 10 次提交
-
-
由 Marek Vasut 提交于
The Gen2 TMU is fed with fixed 32.5 MHz signal from CP . This is then divided by 4 in TMU. Fix the timer clock setting in Gen2. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
Replace those two functions with generic ones by defining the timer macros in include/config/*.h . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
The code uses all in all three TMU registers, drop the massive register layout structures and just define the required timer registers and use them throughout the code. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
The header contains only the TMU register layout, just inline it into the TMU timer implementation and drop the header completely. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
The R-Car Gen2 feeds the TMU with CONFIG_SYS_CLK_FREQ / 2, while the old SH parts use CONFIG_SYS_CLK_FREQ directly. Just put this into the TMU implementation and drop the CONFIG_SH_TMU_CLK_FREQ config option. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
This function just returns CONFIG_SH_TMU_CLK_FREQ, use the constant directly instead. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
These functions are always called for timer = 0, so drop the timer check. Since these functions are called from one place only and they are reduced to one line of code, just inline them. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
The tmu_bit value evaluates to (ffs(4) >> 1) - 1 = (3 >> 1) - 1 = 0. Just drop the tmu_bit completely as well as CONFIG_SYS_TMU_CLK_DIV. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
This constant is always 4 , for all boards that exist. Define it once in arch/sh/lib/time.c and remove it from the configs. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
-
由 Marek Vasut 提交于
Drop the macro as it is never used and it collides with sh_eth.h macros. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-