- A10 FPGA programming support, Gen5 livetree conversion

- SH2, SH3 removal

Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree
functions (inspired from mt7621_gpio.c).
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'socfpga_reset_probe' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int'.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'altera_uart_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'dw_spi_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to
read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to
read flash (child node) parameters.

Tested on socfpga_socrates (socfpga gen5).
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

The dw-apb timer does not use 'gd', so remove its declaration.
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Fix SPI flash environment erase size error.

CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
to allow erase one environment sector.

Fix error below:

SOCFPGA_STRATIX10 # saveenv
Saving Environment to SPI Flash...
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Erasing SPI flash...SF: Erase offset/length not multiple of erase size
Failed (-22)
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL
. The result of calculation is come from default max cluster(0x10000) +
others(0x2000) + additional memory for headroom(0x3000).
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Update the default configuration file to enable the necessary functionality
the get the kit working.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Update the default configuration file to enable the necessary functionality
to get the SoCFPGA loadfs driver support. This would enable the
implementation of programming bitstream into FPGA from MMC.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Mark Jonas <mark.jonas@de.bosch.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

Drop unused macros from the header to clean it up.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

There is no RTS7751R2D support in U-Boot, drop all the RTS7751R2D macros.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

There is no SH2007 support in U-Boot, drop all the SH2007 macros.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

There is no H8 support in U-Boot, drop all the H8 macros.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>

- Correct CONFIG_CRC32 related options in Kconfig
- CONFIG_GPIO select's DM_GPIO, drop CONFIG_GPIO from whitelist.txt

There are no longer any references to this in the code so this can be
removed.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

There is no check for CONFIG_CRC32 so the #define in image.h does
nothing. Remove it.
Reported-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Reviewed-by: NHeiko Schocher <hs@denx.de>

There is no 'config CRC32' remove the select that was attempting to use
it.
Reported-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

There is no 'config CRC32', remove the select that was attempting to use
it.
Reported-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

CONFIG_GPIO does not exist. There is one hit for it in tegra_gpio.c but
it is a variable name.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

CONFIG_GPIO does not exist. sysreset_gpio.c uses the DM gpio APIs so the
correct option to select is DM_GPIO.
Reported-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- Minor fixes (ata memory leak, implement feedback on ohci-da8xx
  changes, avb test fix, mmc test fix, spelling fixes, make FIT really
  optional, fit-dtb blob cleanups, TI K3 workflow improvements, bootz
  can boot barebox on 32bit ARM).

There is one case where 400ms is not sufficient for loading the
system firmware:
- System firmware is not signed with rsa degenerate key.
- ROM loading the sysfw directly from SPI flash which is in memory
  mapped mode.

The above scenario is definitely not desired in production use cases
as it effects boot time. But still keeping this support as this is
a valid boot scenario.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Instead of overlading makefile, use the k3_gen_x509_cert.sh script
to generate boot images.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>