The generated idbloader.img file that rockchip uses should
be not included in git status report
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>

A recent change adjusted the symbol calculation to work on x86 but broke
it for Tegra. In fact this is because they have different needs.

On x86 devices the code is linked to a ROM address and the end-at-4gb
property is used for the image. In this case there is no need to add the
base address of the image, since the base address is already built into
the offset and image-pos properties.

On other devices we must add the base address since the offsets start at
zero.

In addition the base address is currently added to the 'offset' and 'size'
values. It should in fact only be added to 'image-pos', since 'offset' is
relative to its parent and 'size' is not actually an address. This code
should have been adjusted when support for 'image-pos' and 'size' was
added, but it was not.

To correct these problems:
- move the code that handles adding the base address to section.py, which
  can check the end-at-4gb property and which property
  (offset/size/image-pos) is being read
- add the base address only when needed (only for image-pos and not if the
  image uses end-at-4gb)
- add a note to the documentation
- add a separate test to cover x86 behaviour

Fixes: 15c981cc (binman: Correct symbol calculation with non-zero image base)
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>

- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.

- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI

This patch enable TPL support for firefly-rk3288 board, which works ths
same way with other RK3288 board like Tinker, evb.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
as expected. When board_boot_order() `spl-boot-order.c` meets
"same-as-spl", it gets the conf by looking the boot_devices table by boot
source, and parse the node by the conf with:

   node = fdt_path_offset(blob, conf);

which will failed without the "/" indicating the path.

Currently only entries of boot_devices in rk3399 have the "/" prefix.
Therefore add the missing ones in other boards.
Signed-off-by: NLevin Du <djw@t-chip.com.cn>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to
limit the SPL size in 0x40000(start from 0) so that we don't need to do
the relocate for ATF loading.
Note that there will be separate BSS, STACK and MALLOC heap, so the size
0x40000(256KB) should be enough for SPL text.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.

After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Trusted-Firmware can also initialize a secure payload to use as a trusted
execution environment. In general for the arm64 case this is provided as
separate image and uboot is supposed to also place it in a predetermined
location in memory and add the necessary parameters to the ATF boot params.

So add the possibility to get this tee payload from the provided FIT image
and setup things as necessary.

Tested on a Rockchip PX30 with mainline TF-A, mainline OP-Tee (with pending
PX30 support) and mainline 5.4-rc1 Linux kernel.
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

A trusted execution environment should also get loaded as loadable from
a fit image, so add the possibility to present a tee.elf to make_fit_atf.py
that then gets included as additional loadable into the generated its.

For ease of integration the additional loadable is created as atf_(x+1)
after all others to re-use core generation loops.

Tested against the combinations of 1-part-atf and multi-part-atf each
time with and without a tee binary present.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Fix a typo that caused incorrect values to be loaded into the DRAM
controller's deskew registers.
Signed-off-by: NSimon South <simon@simonsouth.net>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Fix a pair of tests in phy_dll_bypass_set() that used incorrect units
for the DDR frequency, causing the DRAM controller to be misconfigured
in most cases.
Signed-off-by: NSimon South <simon@simonsouth.net>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

rk3328 can use same-as-spl option so next loaders are loaded from the same
medium.
Add the boot order in the rock64 dts otherwise booting from sdcard
will result in u-boot looking into the eMMC.
Signed-off-by: NEmmanuel Vadot <manu@freebsd.org>
Reviewed-by: NPeter Robinson <pbrobinson@gmail.com>
Tested-by: NPeter Robinson <pbrobinson@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.
Signed-off-by: NSimon South <simon@simonsouth.net>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply

Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1:
"arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC"
(sha1: 	fc702ed49a8668a17343811ee28214d845bfc5e6)
Signed-off-by: NAndy Yan <andyshrk@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

The RK809 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes)
    - RTC
    - Clocking
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

The RK817 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH)
    - RTC
    - Clocking
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

The RK805 are a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(4*BUCKs, 3*LDOs)
    - RTC
    - Clocking
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

The RK816 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH)
    - RTC
    - Clocking
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

In order to adapt the following pmics, make the interface more compatible.
Support buck and ldo suspend voltage setting and getting.
Supprot buck and ldo suspend enable/disable setting and getting.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

support parse regulator standard property:
regulator-off-in-suspend;
regulator-init-microvolt;
regulator-suspend-microvolt:
 regulator_get_suspend_enable
 regulator_set_suspend_enable
 regulator_get_suspend_value
 regulator_set_suspend_value
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

- Assorted fixes

This script was only used on the MX1ADS board (and possibly other MX1
platforms) to program the flash.  As we no longer have any boards for
that SoC, remove this tool.

Fixes: e570aca9 ("mx1ads: remove board support")
Signed-off-by: NTom Rini <trini@konsulko.com>

- Add Phytium Durian Board
- Assorted bugfixes
- Allow for  make ERR_PTR/PTR_ERR architecture specific

- LogicPD platform fixes
- Adaptive Voltage Scaling (AVS) support
- Minor bugfixes

Due to the commit 4b0bcfa7 ("Kconfig: Migrate CONFIG_BOOTM_* options")
BOOTEFI and BOOTEFI_HELLO_COMPILE (and other BOOTEFI configs) are
displayed in a long distance. This will make it difficult for us to
understand that those configurations are closely related.
Signed-off-by: NAKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry
is missed by
commit 6d825178 ("configs: Don't use SPI_FLASH_BAR as default")
Signed-off-by: NXiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

While getting the 'subarg' of 'hwconfig' env variable in
config_core_prefetch(), if no hwconfig variable is defined,
below warning is received:
WARNING: Calling __hwconfig without a buffer and
	before environment is ready

Fix this by checking 'hwconfig' env variable.
If not found return without further processing.
Signed-off-by: NPankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Tested-by: NMichael Walle <michael@walle.cc>

The xHCI 1.1 version also need set Transfer Type field
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add the missing RGMII PHY modes in which case the MAC has configure its
RGMII settings. The only difference between these modes is the RX and
TX delay configuration. A user might choose any RGMII mode in the device
tree.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The saved ofnode is used by some PHY drivers to access the device tree
node of the PHY.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NAlex Marginean <alexm.osslist@gmail.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The fsl-layerscape already occupies board_late_init(), therefore it is
not possible for a board to have its own board_late_init(). Introduce
fsl_board_late_init() which can be implemented in the board specific
code.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

The clocks are not dependent on the target but only on the SoC.
Therefore, convert the CONFIG_TARGET_x macros to the corresponding
CONFIG_ARCH_x. This will allow other targets to automatically use the
common code. Otherwise every new target would have to add itself to the
"#if defined(CONFIG_TARGET_x) || .." macros.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: NHoria Geanta <horia.geanta@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>