renaming the "mgsuvd" board port into "km8xx", because
there come more similar boards from keymile.
Compiling the mgsuvd board with "make mgsuvd_config"
remains.
Signed-off-by: NHeiko Schocher <hs@denx.de>

Signed-off-by: NHeiko Schocher <hs@denx.de>

- added to keymile-common.h:
  - bootcount support
  - COMMAND HISTORY
  - CONFIG_AUTO_COMPLETE
  - CONFIG_SYS_FLASH_PROTECTION
  - JFFS2 support
  - CONFIG_VERSION_VARIABLE
- extracted common I2C settings for all boards
- common default environment settings summarized
Signed-off-by: NHeiko Schocher <hs@denx.de>

with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache
is not enabled before code runs from RAM.
Signed-off-by: NHeiko Schocher <hs@denx.de>

Size of one environment sector is 0x20000.
Signed-off-by: NHeiko Schocher <hs@denx.de>

Fix indentation broken by symbol renames. "Sort" driver related definitons.
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>

Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

The Nand flash was unable to read and write properly
due to Nand Chip Select (nCE) setup was in reverse
order. Also, increase the Nand time out value to 60.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Update PLATFORM_CPPFLAGS to accept 4.3.x version of
ColdFire compiler.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Default gzip bootm size is 8MB. Some platforms require
more than 8MB
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

The serial boot dram extended/standard mode register was not
setup and was using default DRAM setup causing the U-boot was
unstable to boot up in serial mode.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

According to coldfire manual data timeout > address time out
also use correct macro to program XARB_CFG
Signed-off-by: NArun C <arunedarath@mistralsolutions.com>

This was intended to happen before, but a trivial bug prevented it.
Signed-off-by: NScott Wood <scottwood@freescale.com>

nboot command currently does not skip bad blocks and gives read error when
loading image stored over bad block. With patch applied, nboot works as
expected:

Device 0 bad blocks:
  00780000
  014a0000
  02000000
  02cc0000
  04aa0000

Loading from NAND 128MiB 3,3V 8-bit, offset 0x2c00000
   Image Name:   Linux-2.6.22-omap1
   Created:      2008-11-20  23:44:32 UTC
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    1052520 Bytes =  1 MB
   Load Address: 10008000
   Entry Point:  10008000
Skipping bad block 0x02cc0000
Automatic boot of image at addr 0x10400000 ...
...
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Signed-off-by: NScott Wood <scottwood@freescale.com>

This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with
the DDR2 configuration to only use one CS (rank). As this code is most
likely copied from the original Sequoia version, this error was copied
as well.

This patch also removes some dead code.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with
the DDR2 configuration to only use one CS (rank). As this code is most
likely copied from the original Sequoia version, this error was copied
as well.
Signed-off-by: NStefan Roese <sr@denx.de>

Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D)
specifies that BankSel#1 is not connected, while bootloader memory
configuration is (board/amcc/sequoia/sdram.c):
       mtsdram(DDR0_10, 0x00000300);
i.e. both Chip Selects used - not correct.

If we change to correct value here:
       mtsdram(DDR0_10, 0x00000100);
memory is accessible OK also.
Signed-off-by: NMikhail Zolotaryov <lebon@lebon.org.ua>
Signed-off-by: NStefan Roese <sr@denx.de>

Update CHANEGLOG, fix minor coding style issue.
Signed-off-by: NWolfgang Denk <wd@denx.de>

The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.
Signed-off-by: NGerald Van Baren <vanbaren@cideas.com>
Acked-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.
Signed-off-by: NNorbert van Bolhuis <nvbolhuis@aimvalley.nl>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Read and store OMAP3 die ID in U-Boot environment.
Signed-off-by: NDirk Behme <dirk.behme@googlemail.com>

Set a non-zero speed in the MII register so that MII commands will work.
Signed-off-by: NJon Smirl <jonsmirl@gmail.com>

Signed-off-by: NYusuke Goda <goda.yusuke@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The rtl8139 driver use pci_mem_to_phys. So it need PCI system memory
registration.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

We can built 'make sh7785lcr_32bit_config'. And add new command "pmb"
for this mode. This command changes PMB for using 512MB system memory.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Some register value was hardcoded for System memory size 128MB and
memory offset 0x08000000. This patch fixed the problem.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

It is necessary for some pci device driver.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.

The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.

In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip.  It will silently fall through
onto the generic support.

This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice.  It also makes it explicitly clear that
the generic PHY must be last in the PHY table.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NAndy Fleming <afleming@freescale.com>