The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

We can safely remove it, because none of the currently supported
boards uses these features.

The existing implementation had multiple problems:
   - unnecessary code duplication between sun4i/sun5i/sun7i
   - ZQ calibration was never initiated explicitly, and could be
     only triggered by setting the highest bit in the 'zq' parameter
     in the 'dram_para' struct (this was never actually done for
     any of the known Allwinner devices).
   - even if the ZQ calibration could be started, no attempts were
     made to wait for its completion, or checking whether the
     default automatically initiated ZQ calibration is still
     in progress
   - ODT was only ever enabled on sun4i, but not on sun5i/sun7i

Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.

The impedance and ODT configuration code will be re-introdeced in
one of the next comits.
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.

The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i hardware (even the default register value
0x00c80064 is identical). Except that the counter is ticking a bit
slower on sun7i (3 DRAM clock cycles instead of 2), resulting in
longer actual delays for the same settings.

This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i
SoC variants and not just for sun7i alone. Also an explicit udelay(500)
is added immediately after DDR3 reset for extra safety. This is a
duplicated functionality. But since we don't have perfect documentation,
it may be reasonable to play safe. Half a millisecond boot time increase
is not that significant. Boot time can be always optimized later.
Preferebly by the people, who have the hardware equipment to check the
actual signals on the RESET and CKE lines and verify all the timings.

The old code did not configure the SDR_IDCR register for sun4i/sun5i,
but performed the DDR3 reset very early for sun4i/sun5i. This resulted
in a larger time gap between the DDR3 reset and the DDR3 initialization
steps and reduced the chances of CKE delay timing violation to cause
real troubles.
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.

This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
this means that DRAM is currently in self-refresh mode and retaining the
old data. Since we have no idea what to do in this situation yet, just
set this register to 0 and initialize DRAM in the same way as on any
normal reboot (discarding whatever was stored there).

This part of code was apparently used by the Allwinner boot0 bootloader
to handle resume from the so-called super-standby mode. But this
particular code got somehow mangled on the way from the boot0 bootloader
to the u-boot-sunxi bootloader and has no chance of doing anything even
remotely sane. For example:
1. in the original boot0 code we had "mctl_write_w(SDR_DPCR,
   0x16510000)" (write to the register) and in the u-boot it now looks
   like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the
   register)
2. in the original boot0 code it was issuing three commands "0x12, 0x17,
   0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
   u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry,
   Self-Refresh entry, Refresh)
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of this implementation is that the DQS gating window can be
successfully found for almost every DLL delay adjustment setup that
gets tried. Thus making it unable to see any real difference between
'good' and 'bad' settings.

Also this code was supposed to be only activated by setting the highest
bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board
dram configuration). But none of the linux-sunxi devices has ever used
it for real. Basically, this code is just a dead weight.
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Automatic booting using an extlinux.conf file requires various environment
variables to be set.

Also modify CONFIG_SYS_LOAD_ADDR and CONFIG_STANDALONE_LOAD_ADDR to match
the value chosen for kernel_addr_r, see the added comment for why the new
value is chosen.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Use the new standard bootcmd from <config_distro_bootcmd.h>.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

This generic $bootcmd, and associated support macros, automatically
searches a defined set of storage devices (or network protocols) for an
extlinux configuration file or U-Boot boot script in various standardized
locations. Distros that install such a boot config file/script in those
standard locations will get easy-to-set-up booting on HW that enables
this generic $bootcmd.

Boards can define the set of devices from which boot is attempted, and
the order in which they are attempted. Users may later customize this
set/order by edting $boot_targets.

Users may interrupt the boot process and boot from a specific device
simply by executing e.g.:

$ run bootcmd_mmc1
or:
$ run bootcmd_pxe

This patch was originally written by Dennis Gilmore based on Tegra and
rpi_b boot scripts. I have made the following modifications since then:

* Boards must define the BOOT_TARGET_DEVICES macro in order to specify
  the set of devices (and order) from which to attempt boot. If needed,
  we can define a default directly in config_distro_bootcmd.h.

* Removed $env_import and related variables; nothing used them, and I
  think it's better for boards to pre-load an environment customization
  file using CONFIG_PREBOOT if they need.

* Renamed a bunch of variables to suit my whims:-)
Signed-off-by: NDennis Gilmore <dennis@ausil.us>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Acked-by: NSimon Glass <sjg@chromium.org>

SYS_CPU, SYS_BOARD and SYS_SOC are identical for all sunxi boards, move
them to a shared code block.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

config_distro_defaults.h which is include later will redefine CONFIG_CMD_NET,
drop the useless / meaningless undef of it.

While at also move the undef of CONFIG_CMD_FPGA up to directly under the
include of config_cmd_defaults.h, to make it clear that it overwrites
the setting done from config_cmd_defaults.h .
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

I see no reason to override the choice to include this from
config_cmd_defauls.h .
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

We undef CONFIG_CMD_NET at line 167, and there is nothing re-defining it
between line 167 and the #ifdef CONFIG_CMD_NET, so remove this effectively
dead block.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

sunxi does not need this and it should never have been enabled for it in
the first place.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Signed-off-by: NTom Rini <trini@ti.com>

Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com
Signed-off-by: NAndy Fleming <afleming@gmail.com>

The _config part is gone for sure, the _defconfig target could at least
work. I have not verified this for all targets though.

It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc
alias.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Reflect the latest build system to doc/README.SPL.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

This document is too old and useless.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

This parameter should also be supported.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

Add support for re-relocation malloc() in arm's start-up code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f(). However it is
actually set up before this, it just isn't zeroed.

If we zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change (on arm32 only) to simplify the init process. I
don't have the ability to test aarch64 yet.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NTom Rini <trini@ti.com>

This patch configures the qrio to trigger a core reset on
a CPU reset request.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN
flag in the qrio RESCNF reg is added.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Check the core timer status register (TSR) for watchdog reset,
and and set the QRIO's reset reason flag REASON1[0] accordingly.

This allows the appliction SW to identify the cpu watchdog as a
reset reason, by setting the REASON1[0] flag in the QRIO.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog
flag in the REASON1 reg is added.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The booting of the board is now protected by the CPU watchdog.
A failure during the boot phase will end up in board reset.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When CONFIG_WATCHDOG is defined the board initialization just performs
a WATCHDOG_RESET, an initialization of the watchdog is not done.
This has been modified fot the MPC85xx, the board initialization calls
its watchdog initialitzation allowing for full watchdog configuration
very early in the boot phase.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Function to inititialize the cpu watchdog added.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
[York Sun: Add prototype in watchdog.h]
Reviewed-by: NYork Sun <yorksun@freescale.com>

For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.

The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):

watchdog_period = 1/fTB * 2^x
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

TCR watchdog bit are overwritten when dec interrupt is enabled.
This has been fixed with this patch.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>