- 29 3月, 2017 40 次提交
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由 Thomas Petazzoni 提交于
The PPv2.2 IP has a different TX and RX descriptor layout compared to PPv2.1. In order to prepare for the introduction of PPv2.2 support in mvpp2, this commit adds accessors for the different fields of the TX and RX descriptors, and changes the code to use them. For now, the mvpp2_port argument passed to the accessors is not used, but it will be used in follow-up to update the descriptor according to the version of the IP being used. Apart from the mechanical changes to use the newly introduced accessors, a few other changes, needed to use the accessors, are made: - The mvpp2_txq_inc_put() function now takes a mvpp2_port as first argument, as it is needed to use the accessors. - Similarly, the mvpp2_bm_cookie_build() gains a mvpp2_port first argument, for the same reason. - In mvpp2_rx_error(), instead of accessing the RX descriptor in each case of the switch, we introduce a local variable to store the packet size. - Similarly, in mvpp2_buff_hdr_rx(), we introduce a local "cookie" variable to store the RX descriptor cookie, rather than accessing it from the descriptor each time. - In mvpp2_tx_frag_process() and mvpp2_tx() instead of accessing the packet size from the TX descriptor, we use the actual value available in the function, which is used to set the TX descriptor packet size a few lines before. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
As indicated by Russell King, the mvpp2 driver currently uses a lot "phys" or "phys_addr" to store what really is a DMA address. This commit clarifies this by using "dma" or "dma_addr" where appropriate. This is especially important as we are going to introduce more changes where the distinction between physical address and DMA address will be key. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Some more U-Boot specific 64bit support changes, mostly changing u32 to unsigned long. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The mvpp2 is going to be extended to support the Marvell Armada 7K/8K platform, which is ARM64. As a preparation to this work, this commit enables building the mvpp2 driver on ARM64, by: - Adjusting the Kconfig dependency - Fixing the types used in the driver so that they are 32/64-bits compliant. We use dma_addr_t for DMA addresses, and unsigned long for virtual addresses. It is worth mentioning that after this commit, the driver is for now still only used on 32-bits platforms, and will only work on 32-bits platforms. Changed by Stefan for U-Boot: Removed the Kconfig change as it does not apply to U-Boot this way. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which doesn't compile nicely on 64-bit. Moreover, those definitions are in fact unneeded, since they are always used in combination with a bit mask that ensures only the appropriate bits are modified. Therefore, such definitions should just be set to 0x0. In addition, as suggested by Russell King, we change the _MASK definitions to also use the BIT() macro so that it is clear they are related to the values defined afterwards. For example: #define MVPP2_PRS_RI_L2_CAST_MASK 0x600 #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) becomes #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) #define MVPP2_PRS_RI_L2_UCAST 0x0 #define MVPP2_PRS_RI_L2_MCAST BIT(9) #define MVPP2_PRS_RI_L2_BCAST BIT(10) Because the values (MVPP2_PRS_RI_L2_UCAST, MVPP2_PRS_RI_L2_MCAST and MVPP2_PRS_RI_L2_BCAST) are always applied with MVPP2_PRS_RI_L2_CAST_MASK, and therefore there is no need for MVPP2_PRS_RI_L2_UCAST to be defined as ~(BIT(9) | BIT(10)). It fixes the following warnings when building the driver on a 64-bit platform (which is not possible as of this commit, but will be enabled in a follow-up commit): drivers/net/ethernet/marvell/mvpp2.c: In function ‘mvpp2_prs_mac_promisc_set’: drivers/net/ethernet/marvell/mvpp2.c:524:33: warning: large integer implicitly truncated to unsigned type [-Woverflow] #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) ^ drivers/net/ethernet/marvell/mvpp2.c:1459:33: note: in expansion of macro ‘MVPP2_PRS_RI_L2_UCAST’ mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thomas Petazzoni 提交于
The mvpp2_bm_bufs_add() currently creates a fake cookie by calling mvpp2_bm_cookie_pool_set(), just to be able to call mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID. Instead of doing this convoluted thing, just call mvpp2_bm_pool_put() directly, since we have the BM pool ID. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
check_cache_range() warns that the top boundaries are not properly aligned when flushing or invalidating the buffers and make these operations fail. This gets rid of the warnings: CACHE: Misaligned operation at range ... Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is defined in the bitsperlong.h header. Lets include this header as the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver uses this macro. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Vlad Zakharov 提交于
This commit replaces legacy timer code with usage of arc timer driver. It removes arch/arc/lib/time.c file and selects CONFIG_CLK, CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default. Therefore we remove CONFIG_CLK option from less common axs101 and axs103 defconfigs. Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from axs10x.h, tb100.h and nsim.h configs files as it is no longer required. Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Vlad Zakharov 提交于
We want to use the same device tree blobs in both Linux and U-Boot for ARC boards. Earlier device tree sources in U-Boot were very simplified and hadn't been updated for quite a long period of time. So this commit is the first step on the road to unified device tree blobs. First of all we re-organize device tree sources for AXS10X boards. As AXS101 and AXS103 boards consist of AXS10X motherboard and AXC001 and AXC003 cpu tiles respectively we add corresponding device tree source files: axs10x_mb.dtsi for motherboard, axc001.dtsi and axc003.dtsi for cpu tiles and axs101.dts and axs103.dts to represent actual boards. Also we delete axs10x.dts as it is no longer used. One more important change - we add timer device to ARC skeleton device tree sources as both ARC700 and ARCHS cores contain such timer. We add core_clk nodes to abilis_tb100, nsim, axc001 and axc003 device tree sources as it is referenced via phandle from timer node in common skeleton.dtsi file. Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Vlad Zakharov 提交于
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: NVlad Zakharov <vzakhar@synopsys.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Dirk Eibach 提交于
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x SOC. It boots from SPI-Flash but can be configured to boot from SD-card for factory programming and testing. On board peripherals include: - 2 x GbE - Xilinx Kintex-7 FPGA connected via PCIe - mSATA - USB3 host - Atmel TPM Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: NMario Six <mario.six@gdsys.cc> Signed-off-by: NStefan Roese <sr@denx.de>
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由 mario.six@gdsys.cc 提交于
Certain boards come in different variations by way of utilizing daughter boards, for example. These boards might contain additional chips, which are added to the main board's busses, e.g. I2C. The device tree support for such boards would either, quite naturally, employ the overlay mechanism to add such chips to the tree, or would use one large default device tree, and delete the devices that are actually not present. Regardless of approach, even on the U-Boot level, a modification of the device tree is a prerequisite to have such modular families of boards supported properly. Therefore, we add an option to make the U-Boot device tree (the actual copy later used by the driver model) writeable, and add a callback method that allows boards to modify the device tree at an early stage, at which, hopefully, also the application of device tree overlays will be possible. Signed-off-by: NMario Six <mario.six@gdsys.cc> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This board specific command tests for the presence of a specified PCIe device (via vendor-ID and device-ID). If the device is not detected, this will get printed. If the device is detected, the board will get resetted so that an easy loop test can be done. The board will reboot until the PCIe device is not detected. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Define a board-specific detection pulse-width array for the SerDes PCIe interfaces. If not defined in the board code, the default of currently 2 is used. Values from 0...3 are possible (2 bits). In this case of the theadorable board, PEX interface 0 needs a value of 0 for the detection pulse width so that the PCIe device (Atheros WLAN PCIe device) is consistantly detected. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Tests have shown that on some boards the default width of the configuration pulse for the PEX link detection might lead to non-established PCIe links (link down). Especially under certain conditions (higher temperature) and with specific PCIe devices (in the case on the theadorable board its a Atheros PCIe WLAN device). To enable a board-specific detection pulse width this weak array "serdes_pex_pulse_width[4]" is introduced which can be overwritten if needed by a board-specific version. If the board code does not provide a non-weak version of this variable, the default value will be used. So nothing is changed from the current setup on the supported board. Many thanks to Adam from Marvell for all his insights here and his suggestion about testing with a changed detection pulse width. Signed-off-by: NStefan Roese <sr@denx.de> Suggested-by: NAdam Shobash <adams@marvell.com> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Remove DM_I2C_COMPAT from the board configurations for Armada 37xx platform boards for supressing the buid tim warning. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Bypass XHCI and AHCi board configuration flow on ESPRESSOBin community board. The community board does not have i2c expander and USB VBUS is always on, so the scan for AHCi and USB devices can be faster without unneded configurations. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add initial default configuration for Marvell ESPRESSOBin community board based on Aramda-3720 SoC Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Initial DTS file for Marvell ESPRESSOBin comunity board based on Armada-3720 SoC. The Marvell ESPRESSOBin is a tiny board made by Globalscale and available on KickStarter site. It has dual core Armv8 Marvell SoC (Armada-3720) with 512MB/1GB/2GB DDR3 RAM, mini-PCIe 2.0 slot, single SATA-3 port, USB 2.0 and USB 3.0 interfaces, Gigabit Ethernet switch with 3 ports, micro-SD socket and two 46-pin GPIO connectors. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Implement the board-specific network init function for ESPRESSOBin community board, setting the on-board Topaz switch port to forward mode and allow network connection through any of the available Etherenet ports. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add support for fixed link to NETA driver. This feature requreed for proper support of SFP modules and onboard connected devices like Ethernet switches Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Signed-off-by: NTerry Zhou <bjzhou@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add ability to use board-specific initialization flow to NETA driver (for instance Ethernet switch bring-up) Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Fix the default pin control values in a board-specific function on early board init stage. This fix allows the NETA driver to work in RGMII mode until the full-featured pin control driver gets introduced. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add pin control nodes for North and South bridges to Armada-37xx DT Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Enable mvebu bubt command support on A3720 DB Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Enable support for Marvell Ethernet PHYs on A37xx platforms Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Modify the file names and deifinitions relater to Marvell db-77f3720 board support. Convert these names to more generic armada-37xx platform for future addition of more boards based on the same SoC family. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Igal Liberman <igall@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
The USB device should linked to VBUS regulator through "vbus-supply" DTS property. This patch adds handling for "vbus-supply" property inside the USB device entry for turning on the VBUS regulator upon the host adapter probe. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add default configuration for MACHHIATOBin community board based on Aramda-8040 SoC. Change-Id: Ic6b562065c0929ec338492452f765115c15a6188 Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Rabeeh Khoury 提交于
Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add i2c-1 pin mappings to CP0(master) DTSI file Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0 Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add GPIO nodes to AP-806 and CP-110-master DTSI files. Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Philipp Tomsich 提交于
Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */ }; }; }; This introduces a recursive helper method ScanNode, which is used by ScanTree to recursively parse the entire tree hierarchy. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
We used to get the address of the optionnal ctrl_mod_mmap register as the third memory range of the "reg" property. the linux driver moved to use a syscon instead. In order to keep the DTS as close as possible to that of linux, we move to using a syscon as well. If SYSCON is not supported, the driver reverts to the old way of getting the address from the 3rd memory range Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
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