Fix the following build error caused by patch "powerpc/pcie: add PCIe
version 3.x support":

pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function)
pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function)
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but
the mask omitted the LSB.  This patch provides a 2-bit wide mask.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module. It
includes C293PCIE board, C293PCIE board and C291PCIE board.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: NPo Liu <Po.Liu@freescale.com>
[yorksun: Fixup include/configs/C29XPCIE.h]
Signed-off-by: NYork Sun <yorksun@freescale.com>

The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:

 - 512K L2 Cache/SRAM and 512 KB platform SRAM
 - DDR3/DDR3L 32bit DDR controller
 - One PCI express (x1, x2, x4) Gen 2.0 Controller
 - Trust Architecture 2.0
 - SEC6.0 engine
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NPo Liu <Po.Liu@freescale.com>

B4860 and B4420 has PCIe version 2.4 IP instead of 3.x
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>

T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

1) Add support in B4860 board files for using IDT driver where
   IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
   that generate different refclks for SerDes modules, used this driver
   for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
   for CPRI to work. CPRI works on 122.88MHz and default refclks coming
   on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
   to b4860qds board file, as SerDes1 Refclk1 would come from
   PHY MUX in case of certain protocols, that have been checked here.
   This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

It allows files not in the same path to use this function
as required by B4 board file
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>

Also change the define name SRDS_RSTCTL_SDPD to
SRDS_RSTCTL_SDEN, which stands for SerDes enable
as mentioned in SerDes module guide
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>

Add code for configuring IDT8T49N222A device for various output refclks
    - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with
      alarm and monitoring functions suitable for networking and
      communications applications. It is able to generate wide range of output
      frequencies.
    - In B4860QDS, it has been used to generate different refclks to SerDes modules
    - Programming of these devices are performed by I2C interface.
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.
Signed-off-by: NManish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: NManish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

When a board (slave) boots from SRIO/PCIE, it would get the instructions
from a remote board (master) by SRIO/PCIE interface, and the slave's
u-boot image should be built with the

	SYS_TEXT_BASE=0xFFF80000;

So the u-boot of the slave should avoid the NOR_BOOT branch at the
booting stage.

For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB
entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000",
and with the 4M size as the boot window in NOR_BOOT branch. Because
the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so
the TLB entry will be from base address 0xffc00000 and with 4M size.

Then the u-boot will set TLB entry 14 from base address
"CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial
stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR
= 0xffd00000. So the TLB entry 14 and 15 will be in confliction.

There will be right TLB entries configurations when avoid the
NOR_BOOT branch and set the boot window from 0xfff00000 with 1M
size space.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB.
DDR changed from DDR2 1G to DDR3 2G.
NAND: 128 MiB
Flash: 64 MiB

Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NHaijun Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: NYork Sun <yorksun@freescale.com>

JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: NYork Sun <yorksun@freescale.com>

On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.

Tested on MT36JSF2G72PZ-1G9E1 RDIMM.
Signed-off-by: NYork Sun <yorksun@freescale.com>

RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.
Signed-off-by: NYork Sun <yorksun@freescale.com>

When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0xffffffff together
with normal LAWs will guarantee the address is not mapped to DDR.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
	ECC for DDR is disabled due the procedure to load images
	No board FPGA (QIXIS)
	NOR flash has 32-bit port for higher loading speed
	IFC and I2C timing don't really matter, so set them fast
	No ethernet
Signed-off-by: NYork Sun <yorksun@freescale.com>

The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.
Signed-off-by: NYork Sun <yorksun@freescale.com>

CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: NYork Sun <yorksun@freescale.com>

FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: NYork Sun <yorksun@freescale.com>

For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY

UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor

USB: Two USB2.0 Type A ports

I2C:
   AT24C01B 1K Board EEPROM (8 bit address)

QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232

PCIE:
   One mini-PCIE slot
Signed-off-by: NMichael Johnston <michael.johnston@freescale.com>
Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: NYork Sun <yorksun@freescale.com>

In case only the CONFIG_SYS_I2C_SPEED is set in configuration file,
the CONFIG_SYS_I2C_SOFT_SPEED is defined as CONFIG_SYS_I2C_SPEED.
The CONFIG_SYS_I2C_SOFT_SPEED is then used throughout the driver.

Unfortunatelly, due to a typo in the driver, instead of defining
CONFIG_SYS_I2C_SOFT_SPEED, an CONFIG_SYS_SOFT_I2C_SPEED was defined
and therefore the driver failed to compile. The same applies for
CONFIG_SYS_I2C_SOFT_SLAVE , where the swap happens as well.

This patch fixes the issue.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

This brings U-Boot's cpp invocation into line with the way the Linux
kernel invokes cpp on device trees. Consistency will be useful to ensure
*.dts is portable between the two.

-undef also has the added advantage of not defining "linux", so DT
property names such as "linux,keymap" don't get mangled.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Recent dtc supports #line directives in the input source code, and even
uses them to generate useful line numbers in any messages it emits. Stop
passing -P to cpp, since there's no need any more.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that nothing uses the defines ARCH_CPU_DTS, BOARD_DTS, stop defining
them.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that we assume dtc supports the -i option, we don't need to use
ARCH_CPU_DTS in *.dts{,i}; we simply specify the include filename
directly, and dtc will find it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

*.dts may use #include (via cpp) or /include/ (via dtc; assuming a newer
dtc). The choice is up to the creator of the DT. Create a common variable
DTC_INCDIRS that lists the paths searched by include statements, and
update cpp and dtc invocation to use them.

For cpp, also specify -nostdinc to ensure the same set of paths is
available to both type of include statement.

For dtc, create a new DTC_FLAGS variable to hold all the flags passed to
dtc.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The invocation of dtc is significantly more complex that it could be,
in order to work around an issue on old versions of dtc, which print
a message to stdout every time they run.

Remove this workaround, on the assumption that people have or will
upgrade to a newer version of dtc. This simplifies the build rule
significantly.

Related, split the invocation of cpp and dtc into separate commands
rather than a pipeline, so that if either fail, it is detected. This has
the nice benefit of saving off the result of the pre-processing step,
allowing it to be easily inspected.

Assuming a new enough dtc (which an earlier patch enforces), dtc will
parse #line directives in its input file, and generate correct file and
line numbers in error messages, even though cpp is unconditionally
applied to its input file.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Aside from microblaze, all other SoCs/boards/vendors store their DT files
in board/$vendor/dts/$soc-$board.dts. Move microblaze-generic.dts to this
location for consistency.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NMichal Simek <monstr@monstr.eu>