I2c address is not 0x21 but 0x20. This patch is fixing both revA and
revC boards.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add new ina226 chip present on i2c bus which wasn't on revA.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This is control board on Bitmain Antminer S9.
There are 3 board variables with 256MB, 512MB and 1024MB DDR.
DDR memory is automatically detected with using get_with using
get_ram_size().

Bitmain is using 16MB space for FPGA which is handled via
reserved-memory. Also U-Boot is allocating 16B for storing bootcounts.
Watchdog is started but never service in U-Boot.

SPL MMC is working. SPL NAND is not working because it is not supported
as of now.
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Sync defconfigs.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Initial support for Avnet MiniZed board. Tested UART1 (serial console),
QSPI(Flash), SDHCI1 (eMMC), USB.
Signed-off-by: NIbai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

CMD_UNZIP is already disabled via Kconfig.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is no reason to keep empty config file in the tree that's why
remove it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use live-tree functions.
Reported-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use live-tree functions.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use live-tree functions.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use live-tree functions.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Detect mmc alias at run time for setting up proper boot_targets sequence.
The first target has to correspond with boot mode.

The purpose of this patch is to get rid of CONFIG_ZYNQ_SDHCI0/1
parameters in full U-Boot.
Unfortunately this patch can't remove it because there is missing
mmc implementation for SPL_DM_SEQ_ALIAS.

Also xilinx_zynqmp.h only setup boot commands for mmc0 and mmc1.
It means using aliases with higher number won't work. But switching
between mmc0 and mmc1 should work properly.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>

Existing EEMI version is to as 1.0 (available from xilinx v2018.1
version). Update required API version to match with EEMI API version.

New PMUFW version is required for operations with programmable logic.
Signed-off-by: NRajan Vaja <rajanv@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

ZynqMP emulation platforms are no longer tested and supported that's why
remove macros and code around.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read reset reason reg and show it in log and also save it as variable.
Clearing reset reason when it is read to show only one status
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is no reason to specify header with full soc name.
Symlink is setup automatically (arch -> arch-zynqmp)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add FIT data-position & data-offset property support for bootm,
which were already supported in SPL.
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>

Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use
malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes
to align with the requested alignment.

The original memalign() function will access mchunkptr struct to adjust the
alignment if there is misalignment happen, but mchunkptr struct is not being
initialized before full malloc is initialized. This cause the system crash.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>

SDMMC_CMD_CPSMEN bit is wrongly check and set in
SDMMC_ARG register instead of SDMMC_CMD register.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Use OTP57 and 58 for MAC address
- OTP57 = MAC address  bits [31:0]
- OTP58 = MAC address  bit  [47:32] stored in OTP  LSB's

Use manufacture information in OTP13 to OTP15 to build unique
chip id saved in env variable "serial#"
(used for USB device enumeration)
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add a MISC driver with read and write access to BSEC IP
(Boot and Security and OTP control)
- offset 0: shadowed values
- offset 0x80000000: OTP fuse box values (SAFMEM)
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

The register TAMP_BOOT_CONTEXT is already updated in
get_bootmode() in cpu.c and no need to be done
twice.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add the needed information to enable the debug uart
to have printf before the serial driver probe
(so before probe for clock, pincontrol and reset drivers)

To enable the debug on uart 4 (default console):
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_STM32=y
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add possibility to update the serial parity used.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Implements serial setparity ops to allow uart parity change.
It allows to select ODD, EVEN or NONE parity.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and
USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets.
Sort defines by descendant order.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add support for early debug printf, before the availability of
driver model and device tree support.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- adds reading FMC swap setting from DTB to SDRAM driver
- sets FMC swap for stm32f429-disco board
- changes ram start address to 0x90000000
Signed-off-by: NRadoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>

Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.

Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>

The uart is already initialized prior to relocation,
reinitialization after relocation is unnecessary.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Failure to set the clocks will causes data abort exception when
trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock
setting failed.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The clock and serial nodes are needed before relocation.
This patch ensures that the msm-serial driver will probe
and provide uart output before relocation.
Signed-off-by: NRamon Fried <ramon.fried@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Now that there are more boards defining this it can be removed from the
whitelist.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add a doc comment for pciauto_region_allocate().
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Currently, if we happen to allocate an address requiring 64 bits to a
device only supporting 32-bit BARs, the address eventually gets silently
truncated to 32 bits. Avoid this by adding a new flag to
pciauto_region_allocate() to bail out in such situations.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>

All of the debug output from this file is squished to one line. Fix
it.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NSimon Glass <sjg@chromium.org>