This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.

It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This option protects the printf() functions from overflow.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix a small comment typo.
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

The i386 version of io.h depends on the phys_addr_t type which is defined in
types.h. It wasn't including that explicitly, and was working presumably
because the other files including it had already included types.h themselves
directly or indirectly. This change fixes that.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

The microsecond timer is not currently implemented, but add a dummy
implementation for now.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

The device tree now includes the necessary console configuration
information.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This change adds a pointer to the global data structure in x86 to point to
the device tree. This mirrors an identical pointer in ARM.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a basic driver for the coreboot framebuffer.
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This file is no longer needed for coreboot.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We don't want this for coreboot, so provide a way of compiling it out.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This patch builds upon the recently introduced CBMEM console
feature of coreboot.

CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.

Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.

>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:

vvvvvvvvvvvvvvvvv
SCSI:  AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure  quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^

Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

When __BYTEORDER_HAS_U64__ is not defined, we got warning following:

-----
/tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’:
/tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’
		[-Wimplicit-function-declaration]
-----

Usually, __arch__swab64* required for __fswab64,  __swab64p and __swab64s
is defined.  Therefore, __BYTEORDER_HAS_U64__ is unnecessary.
This removes __BYTEORDER_HAS_U64__.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: NKim Phillips <kim.phillips@freescale.com>

On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not
connected.  When serial cable is not connected, serial error occurs and
some garbage comes in data register.
sh_serial_tstc() in serial_sh.c does not check error status and misunderstand
there is some input data.  It is the reason that autoboot fails.
This patch adds checking error status in sh_serial_tstc().

This patch is based on v2013.01-rc1 tag of u-boot master git.
Signed-off-by: NTetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The function should set BL bit, but it should not clear other flags.
So, the patch uses set_bl_bit() instead of a local asm code.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

We need an extra condition here in case we want to use fdt without the
silent console/cmdline editing/post options. It is easier to just remove
the #ifdef.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Coreboot boards have an LPC TPM connected, so enable this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.
Signed-off-by: NSimon Glass <sjg@chromium.org>

A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NVincent Palatin <vpalatin@chromium.org>
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This prevents the preprocessor from complaining when processing
variadic macros
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NGraeme Russ <graeme.russ@gmail.com>

U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NGraeme Russ <graeme.russ@gmail.com>

coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.

Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

These are available on other architectures, so add them on x86.
Signed-off-by: NSimon Glass <sjg@chromium.org>

ilog2 is required by AHCI driver
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>

So it can be used as a type in struct global_data and remove an ugly typecast
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NMarek Vasut <marex@denx.de>

Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>