1. 09 10月, 2009 1 次提交
  2. 08 10月, 2009 4 次提交
    • J
      relocation: Do not relocate NULL pointers. · afc3ba0f
      Joakim Tjernlund 提交于
      NULL is an absolute value and should not be relocated.
      After this correction code like:
       void weak_fun(void) __attribute__((weak));
       printf("weak_fun:%p\n", weak_fun);
      will still print null after relocation.
      Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
      afc3ba0f
    • P
      85xx: Ensure BSS segment isn't linked at address 0 · 3beb40c2
      Peter Tyser 提交于
      When U-Boot is relocated from flash to RAM pointers are modified
      accordingly.  However, pointers initialzed with NULL values should not
      be modified so that they maintain their intended NULL value.  If the
      BSS segment is linked at address 0 its address will not be
      updated as necessary during relocation.
      
      This is a temporary workaround.  The end goal is to add support to
      U-Boot to dynamically locate the BSS at an arbitrary address at
      runtime.  When the ability to fixup the BSS inteligently is
      added, this workaround can be removed and the 85xx link script
      can put the BSS at a fixed address at link time.
      Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
      3beb40c2
    • D
      tqm5200: Correct comment and code in post_hotkeys_pressed. · 95c44ec4
      Detlev Zundel 提交于
      This fixes the code and the comment according to the original intent of
      doing an intensive memory test when PSC6_3 is pulled low on the STK52xx.
      Notably PORT_CONFIG will be overridden with this correct code now,
      so beware.
      
      The original code only worked by coincidence depending on the PORT_CONFIG
      setting from the header file.  The new code was tested to ensure that the
      (undocumented) memory test still works on the STK52x.
      Signed-off-by: NDetlev Zundel <dzu@denx.de>
      CC: Martin Krause <Martin.Krause@tqs.de>
      
      Minor white-space cleanup.
      Signed-off-by: NWolfgang Denk <wd@denx.de>
      95c44ec4
    • W
      mpc512x: fix fixed_sdram() init code. · da01f534
      Wolfgang Denk 提交于
      Commit 054197ba and later fixes used an array to initialize some of
      the MDDRC parameters; however, the use of an array turned out to be a
      bad idea as it was not possible to correlate structure entries to
      array indices in readable and reliable way. Now we use a struct
      instead, which makes this self-explanatory.
      Signed-off-by: NWolfgang Denk <wd@denx.de>
      da01f534
  3. 07 10月, 2009 7 次提交
  4. 05 10月, 2009 7 次提交
  5. 04 10月, 2009 2 次提交
  6. 03 10月, 2009 14 次提交
  7. 02 10月, 2009 3 次提交
    • M
      ppc4xx: Add SDRAM detection for PMC440 boards · 3b4bd2d7
      Matthias Fuchs 提交于
      This patch adds support to detect the amount of DDR2 SDRAM
      on PMC440 modules. Detection is done by probing through
      a list of available and supported hardware configurations
      from 1GByte down to 256MB.
      
      The static TLB entry is replaced by dynamically created entries.
      Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
      Signed-off-by: NStefan Roese <sr@denx.de>
      3b4bd2d7
    • S
      ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling · fb95169e
      Stefan Roese 提交于
      This patch merges the ECC handling (ECC parity byte writing) into one
      file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
      This exception is because only those PPC's use the completely different
      Denali SDRAM controller core.
      
      Previously we had two routines to generate/write the ECC parity bytes.
      With this patch we now only have one core function left.
      
      Tested on Kilauea (no ECC) and Katmai (with and without ECC).
      Signed-off-by: NStefan Roese <sr@denx.de>
      Cc: Felix Radensky <felix@embedded-sol.com>
      Cc: Grant Erickson <gerickson@nuovations.com>
      Cc: Pieter Voorthuijsen <pv@prodrive.nl>
      fb95169e
    • F
      ppc4xx: Reorganize DDR2 ECC handling · d24bd251
      Felix Radensky 提交于
      Reorganize DDR2 ECC handling to use common code for
      SPD DIMMs and soldered SDRAM. Also, use common code
      to display SDRAM info (ECC, CAS latency) for SPD and
      soldered SDRAM variants.
      Signed-off-by: NFelix Radensky <felix@embedded-sol.com>
      Signed-off-by: NStefan Roese <sr@denx.de>
      d24bd251
  8. 01 10月, 2009 2 次提交