- 26 10月, 2020 2 次提交
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由 Sean Anderson 提交于
Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Sean Anderson 提交于
This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NRick Chen <rick@andestech.com>
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- 22 10月, 2020 5 次提交
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由 Robert Marko 提交于
Add support for the hardware pseudo random number generator found in Qualcomm SoC-s. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Robert Marko 提交于
This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Robert Marko 提交于
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Signed-off-by: NLuka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Patrick Delaunay 提交于
Add the STM32MP1 RNG driver in the list of drivers supported by the STMicroelectronics STM32MP15x series. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Patrick Delaunay 提交于
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP" platform to avoid missing files or drivers supported by the STMicroelectronics series STM32MP15x. This patch adds the rules already used in Linux kernel for ARM/STM32 ARCHITECTURE. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 20 10月, 2020 1 次提交
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由 Chunfeng Yun 提交于
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK, and add myself as a maintainer for it. Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 08 10月, 2020 2 次提交
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由 Sean Anderson 提交于
The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 06 10月, 2020 1 次提交
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由 Heinrich Schuchardt 提交于
Add doc/arch/sandbox.rst to the scope of SANDBOX. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 05 10月, 2020 1 次提交
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由 Claudiu Beznea 提交于
Add basic CPU driver use to retrieve information about CPU itself. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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- 28 9月, 2020 1 次提交
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由 Claudiu Beznea 提交于
Add Microchip PIT64B timer. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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- 19 9月, 2020 2 次提交
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由 Robert Marko 提交于
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Robert Marko 提交于
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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- 17 9月, 2020 3 次提交
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由 Miquel Raynal 提交于
I also followed the development of the SquashFS support in U-Boot as part of Joao Marcos internship, so I would also appreciate receiving new contributions and bug reports related to this topic. Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
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由 Thomas Petazzoni 提交于
As I have followed the development of the SquashFS support in U-Boot as part of Joao Marcos work, it makes sense to get Cc'ed on contributions/bug reports related to the squashfs support. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
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- 10 9月, 2020 2 次提交
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由 Robert Marko 提交于
Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Rayagonda Kokatanur 提交于
Update MAINTAINERS file for new files. Signed-off-by: NRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 08 9月, 2020 1 次提交
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由 Qu Wenruo 提交于
Since the current code base is mostly from btrfs-progs, anyone contributing to U-Boot btrfs code could also help us to improve btrfs-progs and btrfs kernel module. Also add myself as designated reviewer. Signed-off-by: NQu Wenruo <wqu@suse.com> Reviewed-by: NMarek Behún <marek.behun@nic.cz>
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- 01 9月, 2020 1 次提交
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由 Masahiro Yamada 提交于
I am leaving Socionext. Orphan the UniPhier platform until somebody takes the role. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 25 8月, 2020 1 次提交
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由 Anastasiia Lukianenko 提交于
Signed-off-by: NAnastasiia Lukianenko <anastasiia_lukianenko@epam.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 14 8月, 2020 1 次提交
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由 Chia-Wei, Wang 提交于
Update maintainers for Aspeed SoC platforms. Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
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- 08 8月, 2020 4 次提交
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由 Jway Lin 提交于
Add Cortina Access LED controller support for CAxxxx SOCs Signed-off-by: NJway Lin <jway.lin@cortina-access.com> Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Simon Glass <sjg@chromium.org> Add head file fixed link error and remove unused flashing function Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Joao Marcos Costa 提交于
Add Python scripts to test 'ls' and 'load' commands. The scripts generate a SquashFS image and clean the directory after the assertions, or if an exception is raised. Signed-off-by: NJoao Marcos Costa <joaomarcos.costa@bootlin.com>
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由 Joao Marcos Costa 提交于
Add 'ls' and 'load' commands. Signed-off-by: NJoao Marcos Costa <joaomarcos.costa@bootlin.com>
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由 Joao Marcos Costa 提交于
Add support for SquashFS filesystem. Right now, it does not support compression but support for zlib will be added in a follow-up commit. Signed-off-by: NJoao Marcos Costa <joaomarcos.costa@bootlin.com>
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- 29 7月, 2020 3 次提交
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由 Rayagonda Kokatanur 提交于
Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3). Signed-off-by: NRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Stefan Bosch 提交于
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - Configuration changed, mainly several "CONFIG_..." moved from s5p4418_nanopi2.h to s5p4418_nanopi2_defconfig and USB related configs removed because USB is not supported yet. - s5p4418_nanopi2.h: "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. - pinctrl is supported now, therefore "CONFIG_PINCTRL=y" added to s5p4418_nanopi2_defconfig. Signed-off-by: NStefan Bosch <stefan_b@posteo.net>
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由 Robert Marko 提交于
This introduces initial support for the popular Qualcomm IPQ40x8 and IPQ40x9 WiSoC series. IPQ40xx series have 4x Cortex A7 ARM-v7A cores. Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029. IPQ40x8 and IPQ40x9 use the same cores, but differ in addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8) and supported peripherals (IPQ40x8 lacks RGMII, LCD controller and EMMC/SDHCI controllers). IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only by their rated temperatures rates with IPQ402X models being rated for wider temperature ranges. Initially this supports: * Simple clock driver (Only for UART1 now, will be extended) * Pinctrl driver (Supports UARTX and GPIO now, will be extended) * GPIOs already supported by msm_gpio driver with updates * UARTs already supported by serial_msm driver with updates Further peripherals will come in later patches. Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
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- 27 7月, 2020 1 次提交
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由 Zhao Qiang 提交于
According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com> Signed-off-by: NBiwen Li <biwen.li@nxp.com> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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- 18 7月, 2020 2 次提交
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由 Stefan Roese 提交于
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Aaron Williams 提交于
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 09 7月, 2020 1 次提交
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由 Arthur Li 提交于
Add I2C controller support for Cortina Access CAxxxx SoCs Signed-off-by: NArthur Li <arthur.li@cortina-access.com> Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Heiko Schocher <hs@denx.de> Reviewed-by: NHeiko Schocher <hs@denx.de> hs: fixed build error, add include log.h
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- 04 7月, 2020 1 次提交
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由 Heinrich Schuchardt 提交于
Provide unit tests for efi_image_region_add(). Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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- 01 7月, 2020 1 次提交
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由 Sean Anderson 提交于
Due to the large number of clocks, I decided to use the CCF. The overall structure is modeled after the imx code. Clocks parameters are stored in several arrays, and are then instantiated at run-time. There are some translation macros (FOOIFY()) which allow for more dense packing. Signed-off-by: NSean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
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- 18 6月, 2020 1 次提交
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由 Neil Armstrong 提交于
Add the recently added reStructuredText board documentation in the appropriate MAINTAINERS files. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 15 6月, 2020 1 次提交
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由 Heinrich Schuchardt 提交于
Add random number generation APIs to the HTML documentation. Fix style issues. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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- 12 6月, 2020 1 次提交
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由 Heinrich Schuchardt 提交于
Convert README.log to reStructuredText and add it to the generated HTML documentation. Assign doc/develop/logging.rst to the maintainer of LOGGING. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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