- 30 8月, 2016 6 次提交
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由 Bin Meng 提交于
This introduces two board defconfig files for generating EFI 32-bit and 64-bit payloads, to run on QEMU x86 target. With these in place, hopefully buildman will catch any build error with EFI payload support on x86. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Since commit 73c5c399 "Makefile: Drop unnecessary -dtb suffixes", EFI payload does not build anymore. This fixes the build. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a debug() at this point to help figure out what is wrong. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a debug() at this point to help figure out what is wrong. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 28 8月, 2016 13 次提交
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由 Masahiro Yamada 提交于
This will be useful, for example, to load firmware to DRAM and make it visible to other agents. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This is very likely to be necessary for normal use cases. Set its default to 'y' for shorter defconfig files. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The eMMC on sLD3 is assigned with dedicated pins (only multiplexed with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Commit 76c52ce2 ("ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes") missed to increase this config for sLD3. This change is needed to add "u-boot,dm-pre-reloc" to some nodes; more devices are bound, more malloc memory is needed. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The revision of the original support card (rev 3.5, rev 3.6) fits in the 8 bit width revision register. When it was extended in a weird way, it was versioned in the format of "3.6.x" (where it should have been "3.7", of course). What is worse, only the sub-level version "6.x" was recorded in the 8 bit width register, completely ignoring the compatibility of the revision register format. This patch saves madly-versioned support cards by assuming the major version "3" when the MSB 4 bit of the register is read as "6". With this, the support card revision that were displayed as "6.10" is now corrected to "3.6.10". Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This supports the system reset via PSCI for ARMv7 SoCs. Because the system reset is not supported on PSCI 0.1, let's define CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there is no CONFIG to enable it in U-Boot for now.) Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
With this, we can save unnecessary udelay(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
With the CONFIG_DM_MMC_OPS migration, the .set_ios callback can return an integer now. Return an appropriate error value rather than sudden death by BUG(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
No more reason to define this function above the ops structure. Move it near the caller. Also, change its return type to void because it never fails. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Catch up with the DM migration. As struct dm_mmc_ops does not have .init callback, call the init function directly from the probe function. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
They are both only referenced in this file. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 27 8月, 2016 9 次提交
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由 Kever Yang 提交于
This patch add maintainer information for rk3399 evb. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Tony Lindgren 提交于
If we do nand device 0 command in u-boot on a device that has NAND support enabled but no NAND chip, we can get data abort at least on omaps. Fix the issue by replacing the check with nand_info[dev] as suggested by Scott Wood. The check for name existed before because before the array-to-pointer conversion there was no way to directly test nand_info[dev] for emptiness. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Masahiro Yamada 提交于
Most of them are my mistakes. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This is needed to move CONFIG options for the recently-added xtfpga_defconfig. The tarball of the pre-built toolchain can be downloaded from: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Stefan Agner 提交于
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: NStefan Agner <stefan.agner@toradex.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Stefan Agner 提交于
Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Tom Rini 提交于
Use a tab not 8 spaces. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: NLokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: NHeiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: NPaul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: N"Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: NTom Rini <trini@konsulko.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NChin Liang See <clsee@altera.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NPaul Kocialkowski <contact@paulk.fr>
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- 26 8月, 2016 12 次提交
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由 Jens Kuske 提交于
The H3 PLL5 used for DRAM barely manages to lock to the required frequency before DRAM controller starts, sometimes leading to wrong delay-line calibration results. This patch changes the PLL tuning parameters to the same values as boot0 used, which speeds up the locking and fixes the problem. Signed-off-by: NJens Kuske <jenskuske@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
When the backlight's pwm input is connected to a pwm output of the SoC, actually use pwm to drive the backlight. The mean reason for doing this is to fix the backlight turning off for aprox. 1 second while the kernel is booting. This is caused by the kernel actually using pwm to drive the backlight, so that it can dim the backlight. First the pwm driver loads and switches the pinmux for the pin driving the backlight's pwm input to the pwm controller. Then about 1s later the actual backlight driver loads and tells the pwm driver to actually update the pwm settings, which have a power-on-reset value of "off". An additional advantage is that this allows us to initatiate the backlight at 80%, which is the kernel default, avoiding a brightness change while the kernel loads. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Reviewed by: Peter Korsgaard <peter@korsgaard.com>
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由 Hans de Goede 提交于
Add a defconfig and dts file for the Empire Electronix M712 tablet, this is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV wifi chip and a DMART06 (1238a4) accelerometer. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
Sync dts files with the current (Aug 18th 2016) state of Maxime's linux/sunxi/for-next repo. Note this commit also updates configs/MSI_Primo81_defconfig, adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary because the tablet does not have a reachable uart so the dts sync drops its serial0 alias. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
Add a defconfig and dts file for tablets using the generic inet-q972 PCB. Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host, micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot, (mini) power-barrel and an usb wifi module. This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Simon Baatz 提交于
Commit f4db6c97 ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode") added a change to hdr->destaddr when dynamically patching an image for UART boot mode. With this change, kwboot ceases to work on Kirkwood. Thus, let's change hdr->destaddr only when we are patching an image with header version 1 (Orion and Kirkwood use header version 0). Signed-off-by: NSimon Baatz <gmbnomis@gmail.com> Fixes: f4db6c97 ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode") Cc: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
Ensure appropriate error messages are generated. Previously all errors indicated that the serdes was already in use. Now appropriate error messages are given. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
As of commit 88e34e5f ("spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_*") these defines are not used. Remove them to avoid confusion. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
The NAND interface on the Armada-38x series is similar to that on the Armada-XP. The key difference is that the NAND ECC clock ratio is provided via the DFX Server registers instead of the Core Clock. Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
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