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  1. 29 11月, 2017 9 次提交
    • P
      boston: Add u-boot.mcs make target · caead80a
      由 Paul Burton 提交于 
      U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs which generates it using the srec_cat tool available from
the SRecord project, and build it by default when srec_cat is present.
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      caead80a
    • P
      boston: Set CONFIG_SYS_LOAD_ADDR to 0x88000000 · fabcffe9
      由 Paul Burton 提交于 
      Generally we load Linux kernels on Boston boards in the form of FIT
images containing a compressed kernel binary. Linux is linked at
0x80100000 and so we need to decompress the kernel binary to that
address, however this is our default load address which means that
unless explicitly avoided we hit a decompression error as the
uncompressed kernel binary overwrites its compressed version from the
FIT image.

Avoid this by adjusting CONFIG_SYS_LOAD_ADDR to 0x88000000 (or
0xffffffff88000000 for MIPS64 builds) which avoids the address overlap
between compressed & uncompressed kernel binaries.
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      fabcffe9
    • P
      MIPS: Break out of cache loops for unimplemented caches · cc4f3643
      由 Paul Burton 提交于 
      If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      cc4f3643
    • P
      MIPS: Clear instruction hazards in flush_cache() · d8b32697
      由 Paul Burton 提交于 
      When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.

In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      d8b32697
    • P
      MIPS: Ensure cache ops complete in cache maintenance functions · 219c2db3
      由 Paul Burton 提交于 
      A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a device to read memory. This requires that we
place a completion barrier (ie. sync instruction) between the cache ops
and whatever write informs the device to perform DMA.

Whilst strictly speaking this isn't all users of the cache maintenance
functions & we could instead place the barriers in the drivers that
require them, it would be much more invasive to do so than to just have
the barrier be the default by placing it in the cache functions
themselves. The cost is low enough that it shouldn't matter to us in any
rare cases that we use the cache functions when not performing DMA.
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      219c2db3
    • P
      Update Paul Burton's email address · c5bf161f
      由 Paul Burton 提交于 
      MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.
Signed-off-by: NPaul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
      c5bf161f
    • P
      MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds · 73780b01
      由 Paul Burton 提交于 
      The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to
2 or 3 for 32 bit or 64 bit builds respectively. This macro is never
actually used though, so remove the dead code.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      73780b01
    • P
      boston: Remove unused label in lowlevel_display · 64f733d3
      由 Paul Burton 提交于 
      The lowlevel_display() function includes a "1:" label which is never
used. Remove it.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      64f733d3
    • P
      boston: Drop unused return value · 555a6529
      由 Paul Burton 提交于 
      The boston lowlevel_init() function zeroes the return register v0,
despite the function not being expected to return a value & that value
never being used.

Remove the redundant assignment to v0.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
      555a6529
  3. 28 11月, 2017 2 次提交
  5. 27 11月, 2017 15 次提交
  7. 26 11月, 2017 14 次提交