Skip to content

U
U-Boot.Mirror

OS / U-Boot.Mirror

通知 1
Star 0
Fork 0
U
U-Boot.Mirror

体验新版 GitCode，发现更多精彩内容 >>

切换分支/标签
  1. 27 11月, 2012 1 次提交
    • S
      spl/85xx: new SPL support · c97cd1ba
      由 Scott Wood 提交于 
      Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
      c97cd1ba
  3. 23 10月, 2012 5 次提交
  5. 22 10月, 2012 1 次提交
  7. 24 8月, 2012 2 次提交
  9. 29 11月, 2011 1 次提交
  11. 30 9月, 2011 2 次提交
  13. 29 7月, 2011 2 次提交
  15. 22 7月, 2011 1 次提交
  17. 12 7月, 2011 1 次提交
  19. 29 4月, 2011 1 次提交
  21. 05 4月, 2011 1 次提交
  23. 04 4月, 2011 1 次提交
    • D
      powerpc/85xx: Add support for Integrated Flash Controller (IFC) · d789b5f5
      由 Dipen Dudhat 提交于 
      The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
        - Functional muxing of pins between NAND, NOR and GPCM
        - Support memory banks of size 64KByte to 4 GBytes
        - Write protection capability (only for NAND and NOR)
        - Provision of Software Reset
        - Flexible Timing programmability for every chip select
        - NAND Machine
                - x8/ x16 NAND Flash Interface
                - SLC and MLC NAND Flash devices support with
                  configurable
                  page sizes of upto 4KB
                - Internal SRAM of 9KB which is directly mapped and
                  availble at
                  boot time for NAND Boot
                - Configurable block size
                - Boot chip select (CS0) available at system reset
        - NOR Machine
                - Data bus width of 8/16/32
                - Compatible with asynchronous NOR Flash
                - Directly memory mapped
                - Supports address data multiplexed (ADM) NOR device
                - Boot chip select (CS0) available at system reset
        - GPCM Machine (NORMAL GPCM Mode)
                - Support for x8/16/32 bit device
                - Compatible with general purpose addressable device
                  e.g. SRAM, ROM
                - External clock is supported with programmable division
                  ratio
        - GPCM Machine (Generic ASIC Mode)
                - Support for x8/16/32 bit device
                - Address and Data are shared on I/O bus
                - Following Address and Data sequences can be supported
                  on I/O bus
                       - 32 bit I/O: AD
                       - 16 bit I/O: AADD
                       - 8 bit I/O : AAAADDDD
                - Configurable Even/Odd Parity on Address/Data bus
                  supported
Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      d789b5f5
  25. 20 1月, 2011 1 次提交
  27. 14 1月, 2011 3 次提交
  29. 29 11月, 2010 1 次提交
  31. 20 10月, 2010 1 次提交
    • Y
      Add memory test feature for mpc85xx POST. · ebbe11dd
      由 York Sun 提交于 
      The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more
than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
further debugging.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      ebbe11dd
  33. 19 8月, 2010 1 次提交
  35. 20 7月, 2010 1 次提交
  37. 16 7月, 2010 4 次提交
  39. 05 7月, 2010 1 次提交
    • W
      Make sure that argv[] argument pointers are not modified. · 54841ab5
      由 Wolfgang Denk 提交于 
      The hush shell dynamically allocates (and re-allocates) memory for the
argument strings in the "char *argv[]" argument vector passed to
commands.  Any code that modifies these pointers will cause serious
corruption of the malloc data structures and crash U-Boot, so make
sure the compiler can check that no such modifications are being done
by changing the code into "char * const argv[]".

This modification is the result of debugging a strange crash caused
after adding a new command, which used the following argument
processing code which has been working perfectly fine in all Unix
systems since version 6 - but not so in U-Boot:

int main (int argc, char **argv)
{
	while (--argc > 0 && **++argv == '-') {
/* ====> */	while (*++*argv) {
			switch (**argv) {
			case 'd':
				debug++;
				break;
			...
			default:
				usage ();
			}
		}
	}
	...
}

The line marked "====>" will corrupt the malloc data structures and
usually cause U-Boot to crash when the next command gets executed by
the shell.  With the modification, the compiler will prevent this with
an
	error: increment of read-only location '*argv'

N.B.: The code above can be trivially rewritten like this:

	while (--argc > 0 && **++argv == '-') {
		char *arg = *argv;
		while (*++arg) {
			switch (*arg) {
			...
Signed-off-by: NWolfgang Denk <wd@denx.de>
Acked-by: NMike Frysinger <vapier@gentoo.org>
      54841ab5
  41. 27 4月, 2010 2 次提交
  43. 22 4月, 2010 1 次提交
  45. 13 4月, 2010 1 次提交
  47. 03 10月, 2009 4 次提交