- 01 8月, 2016 16 次提交
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由 Simon Glass 提交于
The current code for setting up the toolchain config always writes the new paths to an item called 'toolchain'. This means that it will overwrite any existing toolchain item with the same name. In practice, this means that: buildman --fetch-arch all will fetch all toolchains, but only the path of the final one will be added to the config. This normally works out OK, since most toolchains are the same version (e.g. gcc 4.9) and will be found on the same path. But it is not correct and toolchains for archs which don't use the same version will not function as expected. Adjust the code to use a complete glob of the toolchain path. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
It doesn't make sense to complain about missing toolchains when the --fetch-arch option is being used. The user is presumably aware that there is a toolchain problem and is actively correcting it by running with this option. Refactor the code to avoid printing this confusing message. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The function comment should say 'buildman'. Fix it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
Use colour to make it easier to see what is going on. Also print a message before downloading a new toolchain. Mention --fetch-arch in the message that is shown when there are no available toolchains, since this is the quickest way to resolve the problem. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
When there are no toolchains a warning is printed. But in some cases this is confusing, such as when the user is fetching new toolchains. Adjust the function to supress the warning in this case. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
When buildman is run via a symlink, this test fails. Fix it to work the same way as buildman itself. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
If there is no ~/.buildman file, buildman currently complains and exists. To make things a little more friendly, create an empty one automatically. This will not allow things to be built, but --fetch-arch can be used to handle that. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
Tidy up some problems found by a recent review. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Michal Simek 提交于
Add new Kconfig option to disable arch_fixup_fdt() calls for cases where U-Boot shouldn't update memory setup in DTB file. One example of usage of this option is to boot OS with different memory setup than U-Boot use. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Hans de Goede 提交于
With the recent bug fixes for the sun8i_emac driver all known issues are resolved, so we can re-enable the driver. While at it, also enable the emac on the Orange Pi One. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk> Acked-by: NJagan Teki <jteki@openedev.com>
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由 Hans de Goede 提交于
This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID are always 0 on H3 making it a poor candidate to use as source for the serialnr / mac-address, and the other non constant words (1 and 2) also have quite a few bits which are the same for some boards, This commits switches to using the crc32 of words 1 - 3 to get a more unique value for the mac-address / serialnr. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to the NIC specific bytes of the mac all being 0, which leads to the boards not getting an ipv6 address from the dhcp server. This commits adds a check to ensure this does not happen. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Chen-Yu Tsai 提交于
MACPWR was used to bring the Ethernet PHY out of reset. The designware driver now supports the phy reset gpio binding, so this is no longer needed. In fact in requesting the same GPIO, it makes the designware driver fail to probe. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Chen-Yu Tsai 提交于
sunxi uses a 2 cell phandle for gpio bindings. Also there are no seperate nodes for each pin bank. Add a custom .xlate function to map gpio phandles to the correct pin bank device. This fixes gpio_request_by_name usage. Fixes: 7aa97485 ("dm: sunxi: Modify the GPIO driver to support driver model") Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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- 31 7月, 2016 15 次提交
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由 jk.kernel@gmail.com 提交于
PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is the real vendor name. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for fastboot. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in config_distro_defaults.h, and we don't need them in SPL stage. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
Reduce compilation time for SPL. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to setup sdmmc gpio, otherwise we will hit an error below: =>mmc info blk_get_device: if_type=6, devnum=0: dwmmc@ff0c0000.blk, 6, 0 uclass_find_device_by_seq: 0 -1 uclass_find_device_by_seq: 0 0 - -1 -1 - -1 0 - found uclass_find_device_by_seq: 0 1 - -1 -1 - -1 0 - not found fdtdec_get_int_array: interrupts get_prop_check_min_len: interrupts Buswidth = 1, clock: 0 Buswidth = 1, clock: 400000 Sending CMD0 dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy dwmci_send_cmd: Timeout on data busy This reverts commit 6efeeea7. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 jk.kernel@gmail.com 提交于
Revise config to CONFIG_ROCKCHIP_RK3288_PINCTRL. Signed-off-by: NZiyuan Xu <jk.kernel@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com>
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由 jk.kernel@gmail.com 提交于
Add an extra byte so that this data is not byteswapped. Signed-off-by: NZiyuan Xu <jk.kernel@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com>
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由 John Keeping 提交于
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
Update MAINTAINER files for kylin_rk3036, evb_rk3036. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Angelo Dureghello 提交于
This patch is style-related only, to reformat all the start.S code, actually not following a coherent style inside single files and between different cpu start.S files. Linux format has been respected, as - max line width at 80 columns - one 8 cols tab between asm instructions and operands - inline comments, where any, fixed at col 41 Signed-off-by: NAngelo Dureghello <angelo@sysam.it>
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- 30 7月, 2016 9 次提交
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由 Vignesh R 提交于
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the board connected to TI QSPI IP over CS0. Therefore enable QSPI support. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board connected to TI QSPI over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable CONFIG_SPI_FLASH_BAR to access flash regions above 16MB. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz. Therefore update the spi-max-frequency value of QSPI node for DRA74 and DRA72 evm. This increase flash read speed by ~2MB/s. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
Now that QSPI driver can support 76.8MHz, update the CONFIG_SF_DEFAULT_SPEED to the same value. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Lokesh Vutla 提交于
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Wenyou Yang 提交于
Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
As per commit b545a98f ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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