- 26 9月, 2014 1 次提交
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由 York Sun 提交于
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
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- 25 9月, 2014 12 次提交
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由 York Sun 提交于
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
When booting with SP, RCW resides at the beginning of IFC NOR flash. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 York Sun 提交于
Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 Arnab Basu 提交于
of_bus_default_count_cells can be used to get the #address-cells and #size-cells defined by the current node's parent node. This is required when using of_read_number to read from FDT nodes that can be 32 or 64 bytes depending on values defined by the parent. Signed-off-by: NArnab Basu <arnab.basu@freescale.com> CC: Scott Wood <scottwood@freescale.com>
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由 Arnab Basu 提交于
This is being done so that it can be used outside 'fdt_support.c'. Making life more convenient when reading device node properties that can be 32 or 64 bits long. Signed-off-by: NArnab Basu <arnab.basu@freescale.com> Cc: Scott Wood <scottwood@freescale.com>
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由 York Sun 提交于
The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Add support of NOR and NAND flash for simulator target. Here IFC - CS0: NOR flash IFC - CS1: NAND flash Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Acked-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 24 9月, 2014 6 次提交
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由 Robert Baldyga 提交于
Since dev->req_seq value is initialized from "reg" property of fdt node, there is posibility, that address value contained in fdt is greater than INT_MAX, and then value in dev->req_seq is negative which led to probe() fail. This patch fix this problem by ensuring that req_seq is positive, unless it's one of errno codes. Signed-off-by: NRobert Baldyga <r.baldyga@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Allow serial_find_console_or_panic() to work without a device tree. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The sequence number support in driver model requires device tree control. It should be skipped if CONFIG_OF_CONTROL is not defined, and should not require functions from fdtdec. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The list is supposed to be terminated with a NULL name, but is not. If a board probes a chip which does not appear in the table, U-Boot will crash (at least on sandbox). Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
A merge error ended up repeating a similar sentence twice. Fix it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 23 9月, 2014 1 次提交
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- 22 9月, 2014 3 次提交
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由 Simon Glass 提交于
The get_maintainers script is a useful default, but sometimes is copies too many people, or takes a long time to run. Add an option to disable it and update the README. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This check should now be done whatever mode buildman is running in, since we may be displaying information while building. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- Use _defconfig instead of _config, but still _config is working. - Corrected README.sandbox path in ./README Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 21 9月, 2014 1 次提交
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由 Albert ARIBAUD 提交于
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- 19 9月, 2014 11 次提交
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由 Wu, Josh 提交于
Signed-off-by: NJosh Wu <josh.wu@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wu, Josh 提交于
Signed-off-by: NJosh Wu <josh.wu@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Boris BREZILLON 提交于
Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: NJosh Wu <josh.wu@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: NBo Shen <voice.shen@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: NBo Shen <voice.shen@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
Using CPU_HAS_PCR micro to present the SoC has pcr (peripheral control register). Signed-off-by: NBo Shen <voice.shen@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
When use pcr (peripheral control register), then we won't need to care about the peripheral ID. Signed-off-by: NBo Shen <voice.shen@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
Signed-off-by: NBo Shen <voice.shen@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
Signed-off-by: NBo Shen <voice.shen@atmel.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Bo Shen 提交于
Add NOR flash hardware init function, including SMC and PIO configuration. Signed-off-by: NBo Shen <voice.shen@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wu, Josh 提交于
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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- 18 9月, 2014 5 次提交
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由 Guillaume GARDET 提交于
This patch adds boot script support to am335x_evm Signed-off-by: NGuillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@ti.com>
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由 Guillaume GARDET 提交于
OMAP4: Use generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'. This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards. This allows to use EXT partition instead of FAT, while keeping FAT compatibility. Signed-off-by: NGuillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@ti.com>
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由 Murali Karicheri 提交于
This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NKeegan Garcia <kgarcia@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Masahiro Yamada 提交于
Commit f219e013 (tools: Import Kconfiglib) added SPDX GPL-2.0+ to this library by mistake. It should be ISC. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ulf Magnusson <ulfalizer@gmail.com>
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