- 08 7月, 2014 16 次提交
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由 Masahiro Yamada 提交于
This board is old enough and has no maintainer. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
These boards are old enough and have no maintainers. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
These boards are old enough and have no maintainers. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Jeroen Hofstee 提交于
clang is tempted to inteprete such a condition as a assignment as well. Since it isn't don't use double brackets. cc: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Jeroen Hofstee 提交于
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Wu, Josh 提交于
The option can be used to save the environment in spi flash. Implementation code is already exist in command/env_sf.c. But the documentation is missing. This patch add the details for this option to the README file. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Wu, Josh 提交于
Use get_device_and_partition() is better since: 1. It will call the device initialize function internally. So we can remove the mmc intialization code to save many lines. 2. It is used by fatls/fatload/fatwrite. So saveenv & load env should use it too. 3. It can parse the "D:P", "D", "D:", "D:auto" string to get correct device and partition information by run-time. Also we remove the FAT_ENV_DEVICE and FAT_ENV_PART. We use a string: FAT_ENV_DEVICE_AND_PART. For at91sam9m10g45ek, it is "0". That means use device 0 and if: a)device 0 has no partition table, use the whole device as a FAT file system. b)device 0 has partittion table, use the partition #1. Refer to the commit: 10a37fd7 for details of device & partition string. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
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由 Cooper Jr., Franklin 提交于
* This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
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由 Franklin S. Cooper Jr 提交于
* Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: NFranklin S. Cooper Jr <fcooper@ti.com>
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由 Tom Rini 提交于
Make it clear that we need to load a legacy-formatted (aka uImage) kernel into memory as well as the DT if used before using "spl export". Cc: Yebio Mesfin <ymesfin@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 Felipe Balbi 提交于
J6 EVM can be built with UART3 as console, but currently there's nothing muxing UART3 correctly. Likely this only works because, based on commit log, author was only testing with UART3 boot and - I assume - ROM code leave UART3 correctly muxed in that case. If we want to boot from MMC and still use UART3 as console, then we need to mux those signals correctly. Signed-off-by: NFelipe Balbi <balbi@ti.com>
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由 Masahiro Yamada 提交于
The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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由 Wu, Josh 提交于
In README file, add document for the missing configuration option: CONFIG_ENV_IS_IN_FAT. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
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由 Masahiro Yamada 提交于
Commit 7d89982b stopped creating symbolic link arch/${arch}/include/asm/proc. We do not need to delete it by "make mrproper" any more. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Vasili Galka <vvv444@gmail.com>
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由 Jeroen Hofstee 提交于
The code intends for the CM_DLL_READYST to be set, but actually polls till any bit is set since the logical AND is used instead of the bitwise one is used. Fix it. cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Simon Glass 提交于
We need to subtract two hex numbers. Avoid using strtonum() by doing the subtraction in bc with a suitable input base. Signed-off-by: NSimon Glass <sjg@chromium.org> Reported-by: NVasili Galka <vvv444@gmail.com>
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- 07 7月, 2014 1 次提交
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- 05 7月, 2014 15 次提交
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由 Chin Liang See 提交于
To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: NDetlev Zundel <dzu@denx.de>
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由 Linus Walleij 提交于
Turn on generic board for the integrators, as per the request in the startup message. Everything just works, tested on the Integrator/AP and Integrator/CP. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Stephen Warren 提交于
Serial port, SD card, and LCD all work. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Christian Riesch 提交于
Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>
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由 Shaibal.Dutta 提交于
Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: NShaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Reviewed-by: NDarwin Rambo <drambo@broadcom.com>
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由 Łukasz Dałek 提交于
Enable 'generic board init' for H2200 palmtop. Signed-off-by: NLukasz Dalek <luk0104@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Jeroen Hofstee 提交于
cc: Tom Rini <trini@ti.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Albert ARIBAUD 提交于
Run tools/reformat.py -i -d '-' -s 8 to reorder boards as header comments suggest
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由 Chin Liang See 提交于
Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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由 Chin Liang See 提交于
To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Chin Liang See 提交于
To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Sergey Kostanbaev 提交于
This patch returns back support for old ep93xx processors family Signed-off-by: NSergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
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由 Axel Lin 提交于
In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NStefan Roese <sr@denx.de> Reviewed-by: NVipin Kumar <vipin.kumar@st.com> Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com>
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由 Jeroen Hofstee 提交于
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: NTom Rini <trini@ti.com>
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由 York Sun 提交于
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com> Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
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- 03 7月, 2014 8 次提交
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由 J. German Rivera 提交于
Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com> Signed-off-by: NShruti Kanetkar <Shruti@Freescale.com>
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由 York Sun 提交于
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 York Sun 提交于
Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
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由 J. German Rivera 提交于
This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
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由 Darwin Rambo 提交于
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
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由 Stephen Warren 提交于
Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NYen Lin <yelin@nvidia.com>
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由 Stephen Warren 提交于
The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NYen Lin <yelin@nvidia.com>
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由 Stephen Warren 提交于
I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NYen Lin <yelin@nvidia.com>
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