drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write()
and mw_eeprom_read() have incorrect loop conditions:

	while (len <= 2) {

CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Avoid calling free(addr) twice if the device for ucode is not found.

The problem was indicated by cppcheck.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Freeing a buffer before calling hang() is superfluous. Removing the call
reduces the SPL size.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Update branch and version information of ATF and DDR firmware files to
point to latest releases provided by NXP.

This is especially critical for imx8mp evk, as the ATF support for that
SoC is only available in latest releases.

Align all SoCs from imx8m family to use identical revisions of ATF and
DDR firmware.
Signed-off-by: NAndrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

Calling calloc() for 0 members does not make any sense.
Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally
unreasonable.

The current code will lead to a NULL dereference in bcm6348_iudma_enable().

The assignments for ch_priv->busy_desc are obviously swapped.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Add the command "pwm" for controlling the pwm channels. This
command provides pwm invert/config/enable/disable functionalities
via PWM uclass drivers
Signed-off-by: NPragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This adds basic register access and child regulator binding
for the Monolithic MP5416 Power Management IC which integrates
four DC/DC switching converters and five LDO regulators.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Add the default configuration for the AST2600 EVB.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.

However, currently the patch supports only the booting from
memory-mapped SPI flash.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.

AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

Add controller reset support through the
System Control Unit (SCU) of AST2600 SoC.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

AST2600 has 8 watchdog timers including 8 sets of
32-bit decrement counters, based on 1MHz clock.

A 64-bit reset mask is also supported to specify
which controllers should be reset by the WDT reset.
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.
Signed-off-by: NDylan Hung <dylan_hung@aspeedtech.com>
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: NRyan Chen <ryan_chen@aspeedtech.com>

This patch adds the clock control driver
for the AST2600 SoC.
Signed-off-by: NRyan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>

Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h
Signed-off-by: NKate Liu <kate.liu@cortina-access.com>
Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add Cortina Access parallel Nand support for CAxxxx SOCs
Signed-off-by: NKate Liu <kate.liu@cortina-access.com>
Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
CC: Scott Wood <oss@buserror.net>
Reviewed-by: NTom Rini <trini@konsulko.com>

Disable some unneeded config options and adapt the ident string.

CC: Stefan Roese <sr@denx.de>
Signed-off-by: NHolger Brunck <holger.brunck@hitachi-powergrids.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Our kirkwood device embeds a USB host controller that is now used
on some boards. This enables the support of USB and the corresponding
driver.
Signed-off-by: NHolger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Stefan Roese <sr@denx.de>
Reviewed-by: NStefan Roese <sr@denx.de>

The driver only needs to retrieve the pin for the ACPI info. The driver
itself works without depending on GPIO.
Signed-off-by: NHarm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The pci_mmc.c driver can generate ACPI info and therefore includes
asm/acpi_table.h by proxy. This file does not exist for the ARM
architecture and thus code compilation failed when using this
driver on ARM.
Signed-off-by: NHarm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
QEMU.
Signed-off-by: NHarm Berntsen <harm.berntsen@nedap.com>

Add the topckgen, apmixedsys and infracfg clock driver for the MT8183
SoC.
Signed-off-by: NFabien Parent <fparent@baylibre.com>

mkimage is only able to package aarch32 binaries. Add support for
AArch64 images.

One can create a ARM64 image using the following command line:
mkimage -T mtk_image -a 0x201000 -e 0x201000 -n "media=emmc;arm64=1"
-d bl2.bin bl2.img
Signed-off-by: NFabien Parent <fparent@baylibre.com>

Enable fastboot commands for mt8516 pumpkin board.
Signed-off-by: NFabien Parent <fparent@baylibre.com>

Enable USB gadget on pumpkin. This requires to also enable
BOARD_LATE_INIT since the init is done in board_late_init function.
Signed-off-by: NFabien Parent <fparent@baylibre.com>

Initialize USB device on pumpkin if it is enabled in the config.
Signed-off-by: NFabien Parent <fparent@baylibre.com>

Enable the USB port for MT8516 Pumpkin Board.
Signed-off-by: NFabien Parent <fparent@baylibre.com>

Add support for USB on mt8516 based SoC.
Signed-off-by: NFabien Parent <fparent@baylibre.com>

- R-Car pinctrl updates

- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
  - Select TIMER_EARLY to avoid infinite recursion for Trace.

Pull request for documentation tag doc-2021-04-rc1

* document man-page base command
* move README.fdt-overlays to HTML documentation
* add synopsis for pstore command

- Assorted testing improvements and fixes
- Assorted code cleanups

Remove the leading "0x" from rpc node to fix the below dtc warning:

Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit
address format error, expected "ee200000"
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).

So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.

This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.

This also avoids pin re-muxing to same type that is for example from
command line device is asked to re-probe/select (mmc dev x) we return
early with success in this case as the pin is already muxed.
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>