The spansion_erase currently only works when the sector size is 64KB.
cmd[1] should contain the higher 8 bit of the 24 bit address of the
sector to be erased. Currently it is holding the sector index to be
erased which happens to be the same thing when the sector size is
64KB.
Signed-off-by: NMarc-Andre Hebert <marc-andre.hebert@humanware.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Adds support for Winbond's W25Q64 SPI flash. These devices are used on
(among others) Xilinx' SP601 and SP605 Spartan-6 evaluation boards.
Tested with "sf" commands.
Signed-off-by: NGraeme Smecher <graeme.smecher@mail.mcgill.ca>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The GPIO 16 and 19 reconfiguration should be done once USB is initialized.
So moved the reconfiguration to the USB init  function.
Signed-off-by: NRupjyoti Sarmah <rsarmah@apm.com>
Signed-off-by: NStefan Roese <sr@denx.de>

I accidentally left these hacks in the code while doing the big header
cleanup. Let's remove it now.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch changes the PPC4xx POST UART driver to use the common
NS16550 functions for receiving and sending. Additionally the
local function for SoC divisor setup are removed. Instead the
functions from arch/powerpc/cpu/ppc4xx/4xx_uart.c are used. This
removes code duplication.

Also the common CONFIG_SYS_NS16550_COMx defines are now used
to describe the POST UART's.

And a compile breakage is fixed, introduced by a git merge of
the ppc4xx/next branch into master. Now "ppc4xx.h" is moved to
"asm/ppc4xx.h". Fixed as well with this patch.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes a bug in fdt_fixup_nor_flash_node() when the reg
property has multiple reg tuples, like:

	reg = <0 0x00000000 0x04000000
	       0 0x04000000 0x04000000>;

In this case this function did not update the reg property correctly.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch brings the lwmon5 board support up-to-date. Here a
summary of the changes:

lwmon5 board port related:
- GPIO's changed to control the LSB transmitter
- Reset USB PHY's upon power-up
- Enable CAN upon power-up
- USB init error workaround (errata CHIP_6)
- EBC: Enable burstmode and modify the timings for the GDC memory
- EBC: Speed up NOR flash timings

lwmon5 board POST related:
- Add FPGA memory test
- Add GDC memory test
- DSP POST reworked
- SYSMON POST: Fix handling of negative temperatures
- Add output for sysmon1 POST
- HW-watchdog min. time test reworked

Additionally some coding-style changes were done.
Signed-off-by: NSascha Laue <sascha.laue@liebherr.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add support code for bluestone board wth APM821XX processor based.
This patch includes early board init, misc init, configure EBC,
initializes UIC, MAKEALL, board.cfg and MAINTAINERS file.

Signed-off-by: Tirumala R Marri <tmarri@apm.com
Signed-off-by: NStefan Roese <sr@denx.de>

APM821XX is a new line of SoCs which are derivatives of
PPC44X family of processors. This patch adds support of CPU, cache,
tlb, 32k ocm, bootstraps, PLB and AHB bus.
Signed-off-by: NTirumala R Marri <tmarri@apm.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Roderik Wildenburg <roderik.wildenburg@manroland.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

The OTP code does a little shuffling of arguments that aren't really
necessary, so use a local variable instead to fix build errors now
that the args[] parameter is const.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Building this board for parallel flash fills up the bss section and thus
fails to link, so bump up the monitor size a bit.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rather than use a hardcoded "7", use the new Blackfin global define.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The current size used (256KiB) is smaller than the LDR created for
the bf548-ezkit, so 'run update' doesn't work correctly.  So bump
up the size a bit by making this flexible per-board config.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The board includes:
 * ADSP-BF561 rev. 0.5
 * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG)
 * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell)
 * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB)
 * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB)
 * Spartan6-LX150 (memory-mapped; both PPIs also connected)
 * See http://www.skutek.com/Signed-off-by: NWojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since we're no longer extracting the env from the target ELF file (since
upstream wouldn't take that change), we're back to the problem of cpu
defines not properly propagating to the env setup stage.  So the embedded
env built by the host compiler doesn't match the one that is linked into
the u-boot env.
Reported-by: NVivi Li <vivi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The intention all along was to accept pin names irrelevant of their case.
But I guess I forgot to test/implement support for that.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We need to use the Blackfin BootROM-specific OOB layout when we boot out
of NAND as that is what the on-chip ROM expects.

Also need to increase the monitor size a little to accommodate the extra
NAND code overhead.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We use the lock/unlock options in our default nand code, so enabl
support for the options.
Reported-by: NVivi Li <vivi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NPeter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Let people easily override bootdelay and network settings.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Make the GPIO command usable in a scripting environment by returning
the GPIO value rather than always 0.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Support for the Blackfin System Development Platform (SDP) base module.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NPeter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The input sub command was missing from the help text, and it didn't show
the actual value currently read on the GPIO.  This allows people to read
the value of input pins.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The CONFIG_BFIN_CPU option is largely used in the build system, so move
it out of the board config.h and into the board config.mk.  It'd be nice
to keep everything in the config.h, but the patch to extract that value
early was rejected.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Only the BF561 port was using the common dual core headers, so merge them
into the BF561 specific headers.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Only the BF533 port was using the common extended headers, so merge them
into the BF533 specific headers.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>