Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

This patch moves some board specific NAND configs:
- FROM: generic config file 'ti_armv7_common.h'
- TO:   individual board config files using these configs.
So that each board can independently set the value as per its design.

Following configs are affected in this patch:
  CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
  CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
  CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
  CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>

This patch also updates documentation for few of above NAND configs.
Signed-off-by: NPekon Gupta <pekon@ti.com>

PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
  by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
  merging of common platform code in following commit
      commit a0a37183
      ARM: omap: merge GPMC initialization code for all platform

+-----------------+-----------------------------------------------------------+
| Macro           | Reason for removal                                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE                         |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE                      |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so     |
|                 | configuring GPMC chip-select for smallest allowable       |
|                 | segment (GPMC_SIZE_16M) is enough.                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of    |
|                 | 128MB (GPMC_SIZE_128M)                                    |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR      |  Unused Macros                                            |
| PISMO1_NAND     |                                                           |
| PISMO2_CS0      |                                                           |
| PISMO2_CS1      |                                                           |
| PISMO1_ONENAND  |                                                           |
| PISMO2_NAND_CS0 |                                                           |
| PISMO2_NAND_CS1 |                                                           |
| PISMO1_NOR_BASE |                                                           |
| PISMO1_NAND_BASE|                                                           |
| PISMO2_CS0_BASE |                                                           |
+-----------------+-----------------------------------------------------------+
Signed-off-by: NPekon Gupta <pekon@ti.com>

Fixes commit a0a37183
    ARM: omap: merge GPMC initialization code for all platform

1) NAND device are not directly memory-mapped to CPU address-space, they are
 indirectly accessed via following GPMC registers:
 - GPMC_NAND_COMMAND_x
 - GPMC_NAND_ADDRESS_x
 - GPMC_NAND_DATA_x
 Therefore from CPU's point of view, NAND address-map can be limited to just
 above register addresses. But GPMC chip-select address-map can be configured
 in granularity of 16MB only.
 So this patch uses GPMC_SIZE_16M for all NAND devices.

2) NOR device are directly memory-mapped to CPU address-space, so its
 address-map size depends on actual addressable region in NOR FLASH device.
 So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
 size configuration.
Signed-off-by: NPekon Gupta <pekon@ti.com>

The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

This patch adds Keystone2 k2e_evm evaluation board support.
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Keystone2 K2E SoC has slightly different spl pll settings then
K2HK, so correct this.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Use CONFIG_SOC_KEYSTONE in common places instead of defining
a lot of "if def .. || if def " for different Keystone2 SoC types.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch adds clock definitions and commands to support Keystone2
K2E SOC.
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

It's convenient to hold configurations for DDR3 PHY and EMIF in
separate common place. This patch moves K2HK DDR3 PHY and EMIF
configuration data with different rates and memory size to a common
ddr3_cfg.c file.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

With latest v3.13 kernel, unitrd dt fixup is not needed. However for
older kernel versions such as v3.8/v3.10, it is needed. So to work
with both, add a u-boot env variable that can be set to do dt fixup
for older kernels.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.
Acked-by: NMurali Karicheri <m-maricheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

The SoC related common functions in board.c should be placed to
a common keystone.c arch file.
Acked-by: NMurali Karicheri <m-maricheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.
Acked-by: NMurali Karicheri <m-maricheri2@ti.com>
Signed-off-by: NHao Zhang <hzhang@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>

These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: NPekon Gupta <pekon@ti.com>

Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Tested on TAO3530 board.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: NPekon Gupta <pekon@ti.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Cc: Thomas Weber <thomas.weber@corscience.de>

As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers.  Upon further inspection these
had been touching reserved fields (and having no impact).  These came in
from historical bring-up code and can be discarded.  Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.
Reported-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: NTom Rini <trini@ti.com>
Tested-By: NAsh Charles <ashcharles@gmail.com>

Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>

Add support for NAND gpheader image. TI Keystone2 ROM bootloader
expects 8 bytes of trailing zeroes in the nand u-boot image.
So add zeros at the end of the nand gph image.
Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.

The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.

The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.

Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Add in an init function for the drivers/power framework so we can dump
and read the registers via i2c.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NTom Rini <trini@ti.com>

As this is a weak function that we may override, provide a prototype for
it.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NTom Rini <trini@ti.com>

Set the active_slave to 1 as slave 1 is pinned out in dra72x base board
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>

Add cpsw second slave port pinmux to use it as primary ethernet port
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>

Add support for using the second slave port of cpsw
to be used as primary ethernet.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>