Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

The SPL-DFU feature enable to load and
execute u-boot from RAM over usb from
PC using dfu-util.
Hence dfu-reset should not be issued
when dfu-util -R switch is issued.
Signed-off-by: NRavi Babu <ravibabu@ti.com>

Since SPL_DFU_SUPPORT is depends on SPL_RAM_SUPPORT,
hence select SPL_DFU_SUPPORT only when
SPL_RAM_SUPPORT is chosen.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

This configuration should be valid for all F7 family devices in general.
Here is the regions info:

	- Region0 : 4GB	  : cacheable & executable.
	- Region1 : 512MB : text area	: strogly ordered & executable.
	- Region2 : 512MB : peripherals : device memory & non-executable.
	- Region3 : 512MB : peripherals : device memory & non-executable.
	- Region4 : 512MB : cortexM area: strongly ordered & non-executable.

Higher region number overrides the lower region configuration.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

Cortex-M archs support option memory protection unit (MPU). MPU is used
to set the memory types, attributes, access permissions for different regions,
cache policies of the device.

e.g. using MPU it is possible to configure memory region as device memory
or strongly ordered, memory attributes like execute never, cache policies
like write-back or write-through.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

Data cache memory needs to be disabled before handing over control to
linux kernel. This patch populates the cleanup_before_linux stub.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

Add functionality to flush & invalidate all the dcache using the
prototype declared in common header file.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>
[trini: Add dummy functions for the not-enabled case]
Signed-off-by: NTom Rini <trini@konsulko.com>

am335x_evm SPL is very close to its limit in SRAM space.
Switch to use tiny printf to reclaim some size.
Reviewed-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Enable SPL_DM on all AM335x based TI platforms.

http://patchwork.ozlabs.org/patch/751300/Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

No reason to use a separate load script for am33xx than using
omap-common load script.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

For platforms that don't use device tree in SPL the only
way to mark this driver as 'required by relocation' is
with the DM_FLAG_PRE_RELOC flag. Add this to ensure that
the driver is bound.
Reviewed-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

This is to aid platforms that uses OF_PLATDATA.
Reviewed-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Add debug UART functions to permit omap specific ns16550 to
provide an early debug UART. This is mostly in common with
DEBUG_UART_NS16550 except for Mode definition register which
is required for selecting UART mode(16x auto-baud or 13x mode).
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

Enables the pinctrl-single driver to support 16-bit registers. Only
32-bit registers were supported previously. Reduced width registers are
required for some platforms, such as OMAP.
Signed-off-by: NJames Balean <james@balean.com.au>
Cc: Felix Brack <fb@ltec.ch>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NFelix Brack <fb@ltec.ch>
Tested-by: NFelix Brack <fb@ltec.ch>
Reviewed-by: NSimon Glass <sjg@chromium.org>

In single stage bootmode or falcon boot mode, the SPL shall update the
device tree that we load with the normal fixups done via
arch_fixup_fdt(), when possible (ie we have enough information in this
restricted environment to be able to do that still).  This will include
for example updating them memory nodes.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
[trini: Reword commit message]

Adding support for fdt fixup to update the
memory node in device tree for falcon boot.

This is needed for single stage or falcon
bootmode, to pass memory configuration to
kernel through DT memory node.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>

Enables qspi boot configuration for dra7xx platform.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>

Declare the size of ddr very early in spl, so that this can be
used to enable cache.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NRavi Babu <ravibabu@ti.com>

Move the assignment of board info to global data a bit early which is
safe,
so that ram details can be used to enable caches.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

When OF control is enabled for the SPL stage, nodes are removed from
the DTB to reduce its size. While /chosen is kept, /config is removed.

There's no reason why /chosen should be kept over /config (and as we
would like to put properties into /config that control the SPL stage),
we add '/config' to the list of nodes to be retained for the SPL stage.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This adds documentation on the u-boot,spl-payload-offset property
(which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in
the SPL stage, if present).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

For the RK3399-Q7, we need some flexibility (depending on the feature
set we include in the SPL stage and how large our SPI flash is) in
positioning the SPL payload (i.e. the FIT image containing U-Boot, ATF
and the M0 payload) in our SPI flash.

To avoid having to deal with this through different U-Boot images, we
introduce a the '/config/u-boot,spl-payload-offset' property node
allow it to override the default setting.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This should be uint64_t to match its definition in common.h. Fix it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Similar to what blk_get_device_part_str() does, this patch makes
part_get_info_by_name() return the partition number in case of a match.
This is useful when the partition number is needed and not just the
descriptor.
Signed-off-by: NAlex Deymo <deymo@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update the Android image header format to the latest version published
in AOSP. The original code moved to a new repository, so this patch also
updates the reference to that path.
Signed-off-by: NAlex Deymo <deymo@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Hi,

A kind reminder to look at this patch (already reviewed by Marek and acked by Lukasz), and if possible to put it in the next pull list, or the one after is timing is too short.

Thanks in advance for your time

Best Regards
Nicolas

-----Original Message-----
From: Nicolas LE BAYON
Sent: mardi 25 avril 2017 10:18
To: Nicolas LE BAYON <nicolas.le.bayon@st.com>; u-boot@lists.denx.de; lukma@denx.de; marex@denx.de
Cc: nlebayon@gmail.com; Patrice CHOTARD <patrice.chotard@st.com>; Jean-philippe ROMAIN <jean-philippe.romain@st.com>
Subject: [U-Boot][PATCH v7] usb: gadget: avoid variable name clipping in cb_getvar

From: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Instead of using a fixed-size array to store variable name, preferring a dynamic allocation treats correctly all variable name lengths.
Variable names are growing through releases and features. By this way, name clipping is prevented.
Signed-off-by: NNicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Acked-by: NLukasz Majewski <lukma@denx.de>

This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.

Add mipi dsi configuration for evb-rk3288 device tree.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add grf register define for rk3288 mipi dsi
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add mipi dsi configs for rk3399 evb board
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Enable pwm0 for display of rk3399 evb board. The PWM do not have decicated
interrupt number in dts and can not get periph_id by pinctrl framework. So
init them here.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

plat->size here is used to reserve frame buffer space befor relocation.
our mipi panel use 24 bitwidth, and vop require 32bit align. So the frame
buffer size should be at least 1920*1200*32/8.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Because the bitwidth is different for different display mode, so we need
to set them according to demand.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>