Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a new device tree which has very minimum nodes
- x86 reset
- x86 tsc_timer
- x86 pci
- Slim Bootloader serial
Signed-off-by: NAiden Park <aiden.park@intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.

But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NChristian Gmeiner <christian.gmeiner@gmail.com>

To avoid confusion, let's rename the efi-x86 target to efi-x86_app.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

It is possible to create a generic EFI payload for all x86 boards.
The payload is configured to include as many generic drivers as
possible. All stuff that touches low-level initialization are not
allowed as such is the EFI BIOS's responsibility. Platform specific
drivers (like gpio, spi, etc) are not included.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: NTom Rini <trini@konsulko.com>

This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:

- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add Intel Edison board which is using U-Boot.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park <aiden.park@intel.com>
	Dukjoon Jeon <dukjoon.jeon@intel.com>
	eric.park <eric.park@intel.com>
	Fabien Chereau <fabien.chereau@intel.com>
	Felipe Balbi <felipe.balbi@linux.intel.com>
	Scott D Phillips <scott.d.phillips@intel.com>
	Sebastien Colleur <sebastienx.colleur@intel.com>
	Steve Sakoman <steve.sakoman@intel.com>
	Vincent Tinelli <vincent.tinelli@intel.com>

In case we're building for Intel Edison, we must have 4096 bytes of
zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.

First run sets hardware_id environment variable which is read from
System Controller Unit (SCU).

Serial number (serial# environment variable) is generated based on eMMC
CID.

MAC address on USB network interface is unique to the board but kept the
same all over the time.

Set mac address from U-Boot using following scheme:
	OUI = 02:00:86
	next 3 bytes of MAC address set from eMMC serial number

This allows to have a unique mac address across reboot and flashing.
Signed-off-by: NVincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
[bmeng: Add MAINTAINERS file for Intel Edison board]
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds support for the BayTrail based theadorable-x86-dfi-bt700
board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard.
The main difference to the DFI baseboard is, that it isn't equipped
with a Super IO chip and uses the internal HS SIO UART (memory mapped
PCI based) as the console UART.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds support for the DFI BayTrail BT700 QSeven SoM installed
on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton
NCT6102D Super IO chip providing the UART as console.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
 - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
   SOM-DB5800.
 - 4x USB 2.0 (EHCI)
 - Video
 - SATA
 - Ethernet
 - PCIe
 - Realtek ALC892 HD Audio
   Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
   HDA_SDI0 is set in DT to enable HD Audio codec.
   Pin defaults for codec pin complexs are not changed.

Not supported:
 - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
 - USB 3.0 (XHCI)
 - TPM
Signed-off-by: NGeorge McCollister <george.mccollister@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
Type 6. This patch adds support for it as a coreboot payload.

On board SATA and SPI are functional. On board Ethernet isn't functional
but since it's optional and ties up a PCIe x4 that is otherwise brought
out, this isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.
Signed-off-by: NGeorge McCollister <george.mccollister@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

This contains just enough to bring up the serial UART.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
   https://patchwork.ozlabs.org/patch/479745/

Support running U-Boot as a coreboot payload. Tested peripherals include:

- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash

USB3 does not work. This may be a problem with the USB3 PCI driver or
something in the USB3 stack and has not been investigated So far this is
disabled. The SD card slot also does not work.

For video, coreboot will need to run the OPROM to set this up.

With this board, bare support (running without coreboot) is not available
as yet.
Signed-off-by: NSimon Glass <sjg@chromium.org>

New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

No board is using alex.dts, so remove it.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: NSimon Glass <sjg@chromium.org>

It is convenient to have all device trees on the same SoC compiled.
It allows for later easy repackaging without the need to re-run
the make file.

  - Build device trees with the same SoC under arch/$(ARCH)/dts

  - Copy the one specified by CONFIG_DEFAULT_DEVICE_TREE or
    DEVICE_TREE=... to dts/dt.dtb
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>