MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: NYork Sun <yorksun@freescale.com>

LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: NYork Sun <yorksun@freescale.com>

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The agreed split of the top of memory is 256M for debug server and 256M
 for MC. This patch implements the split.

 In addition, the MC mem must be 512MB aligned, so the amount of memory
 to hide must be 512MB to achieve that alignment.
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).

This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add support for reset_cpu() by asserting RESET_REQ_B.
Signed-off-by: Npankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>

Freescale's Layerscape Management Complex (MC) provide support various
objects like DPRC, DPNI, DPBP and DPIO.
Where:
	DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO
	DPBP: Management of buffer pool
	DPIO: Used for used to QBMan portal
	DPNI: Represents standard network interface

These objects are used for DPAA ethernet drivers.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NGeoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NCristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: Npankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:

MC DDR region start = Top of DDR - area reserved by Debug Server FW
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LS2085A and its variants can have up to four clusters. It is safe
to enable timebase for all even some may be disabled.
Signed-off-by: NYork Sun <yorksun@freescale.com>

This function can fail if the device tree runs out of space. Rather than
silently booting with an incomplete device tree, allow the failure to be
detected.

Unfortunately this involves changing a lot of places in the code. I have
not changed behvaiour to return an error where one is not currently
returned, to avoid unexpected breakage.

Eventually it would be nice to allow boards to register functions to be
called to update the device tree. This would avoid all the many functions
to do this. However it's not clear yet if this should be done using driver
model or with a linker list. This work is left for later.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NAnatolij Gustschin <agust@denx.de>

Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.

Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NArnab Basu <arnab.basu@freescale.com>

DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: NYork Sun <yorksun@freescale.com>

LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.

So, update gd->env_addr to reflect correct address.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>