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  1. 23 4月, 2014 3 次提交
  3. 18 4月, 2014 11 次提交
  5. 12 3月, 2014 1 次提交
  7. 11 3月, 2014 2 次提交
    • T
      boards.cfg: Run the reformatter script · f351eb0f
      由 Tom Rini 提交于 
      Some recent changes got parts of the file out of order again, correct.
Signed-off-by: NTom Rini <trini@ti.com>
      f351eb0f
    • M
      boards.cfg: move boards with invalid emails to Orphan · 31f1b654
      由 Masahiro Yamada 提交于 
      When I cc board maintainers, some of them result in
bounce mails.

It turned out the following do not work any more:
  Yuli Barcohen <yuli@arabellasw.com>
  Travis Sawyer <travis.sawyer@sandburst.com>
  Yusdi Santoso <yusdi_santoso@adaptec.com>
  David Updegraff <dave@cray.com>
  Sangmoon Kim <dogoil@etinsys.com>
  Anton Vorontsov <avorontsov@ru.mvista.com>
  Blackfin Team <u-boot-devel@blackfin.uclinux.org>
  Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
  Andre Schwarz <andre.schwarz@matrix-vision.de>

For the blackfin boards where Sonic Zhang is also listed
as a maintainer, dead addresses should be simply dropped.

For all of the others, the status should be changed to "Orphan".

We have adopted the definition of "Orphan" as:
board is not actively maintained any more but still builds, and any
address associated with it is that of the last known maintainer(s)

Even though the emails do not work any more, they carry information.
We want to keep them.

Besides, Orphan boards have been collected at the bottom of boards.cfg.
(This is done when we run "tools/reformat.py")

Add separators to distinguish them from those which
were moved to Orphan 6 months ago.
I believe it will be helpful in future to find which boards are
old enough to be removed from the code base.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      31f1b654
  9. 10 3月, 2014 2 次提交
  11. 08 3月, 2014 1 次提交
    • S
      powerpc/t2080rdb: Add T2080PCIe-RDB board support · 8d67c368
      由 Shengzhou Liu 提交于 
      T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.

T2080PCIe-RDB Feature Overview
------------------------------
Processor:
 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
 - Single memory controller capable of supporting DDR3 and DDR3-LP devices
 - 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
 - Two 10M/100M/1G RGMII ports on-board
 - Two 10Gbps SFP+ ports on-board
 - Two 10Gbps Base-T ports on-board
Accelerator:
 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
 - SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
 - NOR:  128MB 16-bit NOR flash
 - NAND: 512MB 8-bit NAND flash
 - CPLD: for system controlling with programable header on-board
eSPI:
 - 64MB N25Q512 SPI flash
USB:
 - Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
 - One PCIe x4 gold-finger
 - One PCIe x4 connector
 - One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
 - Two SATA 2.0 ports on-board
SDHC:
 - support a TF-card on-board
I2C:
 - Four I2C controllers.
UART:
 - Dual 4-pins UART serial ports
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>
      8d67c368
  13. 07 3月, 2014 2 次提交
  15. 05 3月, 2014 1 次提交
  17. 25 2月, 2014 1 次提交
    • S
      powerpc/t2081qds: Add T2081 QDS board support · 254887a5
      由 Shengzhou Liu 提交于 
      T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>
      254887a5
  19. 24 2月, 2014 1 次提交
  21. 23 2月, 2014 1 次提交
  23. 22 2月, 2014 5 次提交
  25. 14 2月, 2014 1 次提交
    • G
      arm/km: introduce kmsugp1 target · 9c134e18
      由 Gerlando Falauto 提交于 
      KMSUGP1 is from a u-boot perspective (almost) identical to KMNUSA.
The only difference is that the PCIe reset is connected to Kirkwood pin
MPP7_PEX_RST_OUTn, we use a dedicated config flag KM_PCIE_RESET_MPP7.
Such pin should theoretically be handled by the PCIe subsystem
automatically, but this turned out not to be the case.
So simply configure this PIN as a GPIO and issue a pulse manually.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
Cc: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Cc: Valentin Longchamp <valenting.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: NValentin Longchamp <valentin.longchamp@keymile.com>
      9c134e18
  27. 07 2月, 2014 2 次提交
    • A
      arc: add AXS101 board support · a7069ddf
      由 Alexey Brodkin 提交于 
      AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:

 * DW APB UART
 * DW Mobile Storage (MMC/SD)
 * DW I2C
 * DW GMAC
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
      a7069ddf
    • A
      arc: add Arcangel4 board support · 66712b8b
      由 Alexey Brodkin 提交于 
      Arcangel4 is a FPGA-based development board that is used for prototyping and
verificationof of both ARC hardware (CPUs) and software running upon CPU.

This board avaialble in 2 flavours:
 * Little-endian (arcangel4)
 * Big-endian (arcangel4-be)
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
      66712b8b
  29. 06 2月, 2014 5 次提交
  31. 04 2月, 2014 1 次提交