- 08 10月, 2021 22 次提交
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由 Robert Marko 提交于
Since the CP1 pinctrl is not properly set in the DTS, there is no need for setting the pinctrl by writing hardcoded values to the MPP registers. So, drop the code relating to that. Fixes: 87c220d0 ("arm: mvebu: mvebu_armada-8k: Add support for initializing iEi Puzzle-M801 networking") Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Robert Marko 提交于
Current CP1 pinctrl that is set on the Puzzle M801 is incorrect. CP1 pins are only used for the SMI bus and the MSS I2C, all other pins are just GPIO-s. Due to this being set completely wrong, the pinctrl was actually ended up being hardcoded in the board_early_init_f() step so that SMI would work. That is obviously not the right thing to do, so convert the register hex values that were being written to individual pin modes and set it in the DTS. Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does not get probed without an consumer. Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support") Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig, as this was removed from mach/config.h in a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig"). Signed-off-by: NStefan Roese <sr@denx.de> Fixes: a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig") Cc: Tom Rini <trini@konsulko.com> Cc: Marek Behún <kabel@kernel.org> Cc: Pali Rohár <pali@kernel.org> Tested-by: NPali Rohár <pali@kernel.org>
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由 Marek Behún 提交于
There were several changes for this structure but the documentation was not changed at the time. Fix this. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Update indentation in driver's private structure. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Now that PCI Bridge is working for the PCIe Root Port, U-Boot's PCI_PNP code automatically enables memory access and bus mastering when needed. We do not need to enable it when setting the HW up. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Aardvark does not have a real PCIe Root Port device on the root bus. Instead it has PCIe registers of PCIe Root Port device mapped in internal Aardvark memory space starting at offset 0xc0. The PCIe Root Port itself is normally available as a PCI Bridge device on the root bus with bus number zero. Aardvark instead has the configuration registers of this PCI Bridge at offset 0x00 of Aardvark's memory space, but the class code of this device is Mass Storage Controller (0x010400), instead of PCI Bridge (0x600400), which causes U-Boot to fail to recognize it as a P2P Bridge Add a hook into the pcie_advk_read_config() / pcie_advk_write_config() functions to redirect access for root bus from PIO transfer to this internal Aardvark memory space. This will allow U-Boot to access configuration space of this PCI Bridge which represents PCIe Root Port. Redirect access to PCI Bridge registers in range 0x10 - 0x34 to driver's internal buffer (cfgcache[]). This is because at those addresses Aardvark has different registers, incompatible with config space of a PCI Bridge. Redirect access to PCI Bridge register PCI_ROM_ADDRESS1 (0x38) to Aardvark internal address for that register (0x30). When reading PCI Bridge register PCI_HEADER_TYPE, set it explicitly to value Type 1 (PCI_HEADER_TYPE_BRIDGE) as PCI Bridge must be of Type 1. When writing to PCI_PRIMARY_BUS or PCI_SECONDARY_BUS registers on this PCI Bridge, correctly update driver's first_busno and sec_busno variables, so that pcie_advk_addr_valid() function can check if address of any device behind the root bus is valid and that PIO transfers are started with correct config type (1 vs 0), which is required for accessing devices behind some PCI bridge after the root bus. U-Boot's PCI_PNP code sets primary and secondary bus numbers as relative to the configured bus number of the root bus. This is done so that U-Boot can support multiple PCIe host bridges or multiple root port buses, when internal bus numbers are different. Now that root bus is available, update code in pcie_advk_read_config() and pcie_advk_write_config() functions to correctly calculate real Aardvark bus number of the target device from U-Boot's bus number as: busno = PCI_BUS(bdf) - dev_seq(bus) Stefan: Small fix of header masking as suggested by Pali. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Aardvark reports Disabled and Hot Reset LTSSM states as values >= 0x20. Link is not up in these states, so fix pcie_advk_link_up() function. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Remove unused PCIe functions from SerDes code. They are unused and are duplicated either from generic PCIe code or from pci_mvebu.c. Remove also unused PCIe macros from SerDes code. They are just obfuscated variants of standards macros in include/pci.h or in pci_mvebu.c. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
This code is trying to parse PCIe config space of PCIe card connected on the other end of link and then is trying to force 5.0 GT/s speed via Target Link Speed bits in PCIe Root Port Link Control 2 Register on the local part of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in Link Capabilities Register. The code is incorrect for more reasons: - Accessing config space of an endpoint card cannot be done immediately. If the PCIe link is not up, reading vendor/device ID registers will return all ones. - Parsing is incomplete, so it can cause issues even for working cards. Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from 2.5 GT/s to 5.0 GT/s autonomously when it is supported. Most importantly, this code does not change link speed at all, since because after updating Target Link Speed bits on PCIe Root Port Link Control 2 Register, it is required to retrain the link, and the code for that is completely missing. The code was probably needed for making buggy endpoint cards work. Such a workaround, though, should be implemented via PCIe subsystem (via quirks, for example), as buggy cards could also affect other PCIe controllers. Note that this code is fully unrelated to a38x SerDes code and really should not have been included in SerDes initialization. Usage of magic constants without names and comments made this SerDes code hard to read and understand. Remove this PCIe application code from low level SerDes code. As this code is configuring only 5.0 GT/s part, in the worst case, it could leave buggy cards at the initial speed of 2.5 GT/s (if somehow before this change they could have been "upgraded" to 5.0 GT/s speed even with missing link retraining). Compliant cards which just need longer initialization should work better after this change. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
PCI device ID is part of the PCIe controller SoC / revision. For Root Complex mode (which is the default and the only mode supported currently by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device. If there is some issue with this device ID, it should be set / updated by PCIe controller driver (pci_mvebu.c), as this register resides in address space of the controller. It shouldn't be done in SerDes initialization code. In the worst case (a specific board for example) it could be done via U-Boot's weak function board_pex_config(). But it should not be overwritten globally for all A38x devices. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Enabling Common Clock Configuration bit in PCIe Root Port Link Control Register should not be done unconditionally. It is enabled by operating system as part of ASPM. Also after enabling Common Clock Configuration it is required to do more work, like retraining link. Some cards may be broken due to this incomplete Common Clock Configuration and some cards are broken and do not support ASPM at all. Remove this incomplete code for Common Clock Configuration. It really should not be done in SerDes code as it is not related to SerDes, but to PCIe subsystem. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register are read-only SAR registers and are initialized according to current mode configured by PCIe controller. Changing PCIe controller mode (from Root Complex mode to Endpoint mode or the other way) is possible via PCI Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This has to be done in PCIe controller driver (in our case pci_mvebu.c). Note that default mode is Root Complex. Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are platform specific and overwriting them does not make sense. They are set by PCIe controller according to current SerDes configuration. For A38x it is 5.0 GT/s if SerDes supports appropriate speed. Maximum Link Width bits of PCIe Root Port Link Capabilities Register are read-only SAR registers, but unfortunately if this is not set correctly here, then access PCI config space of the endpoint card behind this Root Port does not work. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Add comments to understand what this magic code is doing. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
SoC Control 1 Register (offset 0x18204) is already defined by macro SOC_CONTROL_REG1. Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c code and remove the other definition. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Replace magic register offsets by macros to make code more readable. Add comments about what this code is doing. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
phy_txd_inv or phy_rxd_inv needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408Signed-off-by: NPali Rohár <pali@kernel.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Pali Rohár 提交于
Commit 079b35a2 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal possible size for allocated 128 MiB PCIe window. PCIe IO size in that commit was unchanged. Armada 3720 PCIe controller supports 32-bit IO space mapping so it is possible to assign more than 64 KiB if address space for IO. Currently controller has assigned 127 MiB + 64 KiB memory and therefore there is 960 KiB of unused memory. So assign it to IO space by increasing IO window from 64 KiB to 1 MiB. Signed-off-by: NPali Rohár <pali@kernel.org> Fixes: 079b35a2 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB") Reviewed-by: NStefan Roese <sr@denx.de>
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- 07 10月, 2021 18 次提交
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https://source.denx.de/u-boot/custodians/u-boot-amlogic由 Tom Rini 提交于
- Add new SoC ID for S905Y2 found in Radxa Zero - pcie_dw_meson: fix usb fail when pci link fails to go up - Sync Amlogic DT from Linux 5.14 - dwc3-meson-gxl: add AXG compatible - dts: keep back HW order for MMC devices since change in Upstream Linux - Cleanup local AXG DT USB nodes now everything is upstream - distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot - New Boards: - Odroid-HC4: a variant of Odroid-C4 with 2 SATA ports (via PCIe-SATA bridge) - Beelink GS-King X: A variant of the other Beelink board with 2 SATA ports (via USB3-SATA bridge) - Banana Pi M5: another credit card SBC - JetHub D1/H1: home automation controllers - Radxa Zero: another RPi Zero sized SBC
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https://source.denx.de/u-boot/custodians/u-boot-riscv由 Tom Rini 提交于
- Reset improvements, enable coherence manager on ae350, k210 clk improvements, other fixes
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由 Christian Hewitt 提交于
Add documentation bits for the Radxa Zero Signed-off-by: NChristian Hewitt <christianshewitt@gmail.com> [narmstrong: updated u200 MAINTAINERS] Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Christian Hewitt 提交于
Add a defconfig for the Radxa Zero SBC, using an Amlogic S905Y2 chip. Signed-off-by: NChristian Hewitt <christianshewitt@gmail.com> [narmstrong: updated u200 MAINTAINERS & add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Christian Hewitt 提交于
Import the initial dts queued for Linux 5.16.y Signed-off-by: NChristian Hewitt <christianshewitt@gmail.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Christian Hewitt 提交于
Alpha sort the Amlogic dtb list (same as the kernel). Signed-off-by: NChristian Hewitt <christianshewitt@gmail.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Vyacheslav Bocharov 提交于
Fix doc/board/amlogic/index.rst: - Add S905W to S905X column. - Add JetHub devices to the corresponding columns. - Fix tabs to spaces for table alignment Add doc/board/amlogic files: - jethub-j100.rst - jethub-j80.rst Signed-off-by: NVyacheslav Bocharov <adeep@lexina.in> Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Vyacheslav Bocharov 提交于
Add support for new home automation devices. JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller with the following features: - DIN Rail Mounting case - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz - no video out - 512Mb/1GB DDR3 - 8/16GB eMMC flash - 1 x USB 2.0 - 1 x 10/100Mbps ethernet - WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE 802.11a/b/g/n/ac, Bluetooth 4.2. - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support. - 2 x gpio LEDS - GPIO user Button - 1 x 1-Wire - 2 x RS-485 - 4 x dry contact digital GPIO inputs - 3 x relay GPIO outputs - DC source with a voltage of 9 to 56 V / Passive POE JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller with the following features: - Square plastic case - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz - no video out - 1GB DDR3 - 8/16GB eMMC flash - 2 x USB 2.0 - 1 x 10/100Mbps ethernet - WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0. - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support. - MicroSD 2.x/3.x/4.x DS/HS cards. - 1 x gpio LED - ADC user Button - DC source 5V microUSB with serial console Patches from: - JetHub H1 https://lore.kernel.org/r/20210915085715.1134940-4-adeep@lexina.in https://git.kernel.org/amlogic/c/abfaae24ecf3e7f00508b60fa05e2b6789b8f607 - JetHub D1 https://lore.kernel.org/r/20210915085715.1134940-5-adeep@lexina.in https://git.kernel.org/amlogic/c/8e279fb2903990cc6296ec56b3b80b2f854b6c79Signed-off-by: NVyacheslav Bocharov <adeep@lexina.in> Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> [narmstrong: removed unused variable value] Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Vyacheslav Bocharov 提交于
JetHub devices uses its own boot sequence with "rescue" button Signed-off-by: NVyacheslav Bocharov <adeep@lexina.in> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
Banana Pi BPI-M5 is a credit card format SBC with the following features: - Amlogic S905X3 quad core Cortex-A55 - Mali-G31 GPU - 4GB LPDDR4 - 16GB eMMC flash - 4 USB 3.0 - 1 GbE ethernet - HDMI output - 2x LEDS - SDCard - 2.5mm Jack with Stereo Audio + CVBS - Infrared Received - ADC Button - GPIO Button - 40 pins header + 3pins debug header [narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The Beelink GS-King X is a variant of the GS King boards but with an internal USB to SATA bridge and advanced audio features. [narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
Add documentation bits for the Odroid-HC4. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The Odroid-HC4 is a variant of the Odroid-C4 board but with a PCIe-SATA bridge instead of the USB3 ports. [narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The SCSI device can be a PCIe adapter, so run pcie enum if enabled. Signed-off-by: NMark Kettenis <kettenis@openbsd.org> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
Add SCSI target to be able to boot from the SATA disks on the Odroid HC4 using an on-board AHCI PCIe controller. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NMark Kettenis <kettenis@openbsd.org>
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由 Neil Armstrong 提交于
Drop the local USB nodes after Linux 5.14 sync. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
Since Linux commmit [1], the order is fixed with aliases, in order to keep the MMC device order, set it back to HW order in U-Boot dtsi files. [1] ab547c4fb39f ("arm64: dts: amlogic: Assign a fixed index to mmc devices") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
Upstream Linux uses the "amlogic,meson-axg-usb-ctrl" for AXG SoCs. This adds it to the compatible list for this driver. Reported-by: NVyacheslav Bocharov <adeep@lexina.in> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Tested-by: NVyacheslav Bocharov <adeep@lexina.in>
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