- 18 2月, 2009 3 次提交
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由 Mike Frysinger 提交于
The CONFIG_CMD_ENV option controls enablement of the `saveenv` command rather than a generic "env" command, or anything else related to the environment. So, let's make sure the define is named accordingly. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Valeriy Glushkov 提交于
Default CONFIG_CMD_IMLS must be disabled when CONFIG_SYS_NO_FLASH is defined Signed-off-by: NValeriy Glushkov <gvv@lstec.com>
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由 Rafal Jaworowski 提交于
- Extend ub_dev_read() and ub_dev_recv() so they return the length actually read, which allows for better control and error handling (this introduces additional error code API_ESYSC returned by the glue mid-layer). - Clean up definitions naming and usage. - Other minor cosmetics. Note these changes do not touch the API proper, so the interface between U-Boot and standalone applications remains unchanged. Signed-off-by: NRafal Jaworowski <raj@semihalf.com>
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- 17 2月, 2009 19 次提交
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由 Wolfgang Denk 提交于
After introducing redundant environment the kernel images was overlapping with environment. Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Andy Fleming 提交于
Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
This uses the new MMC framework Some contributions by Dave Liu <daveliu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
Here's a new framework (based roughly off the linux one) for managing MMC controllers. It handles all of the standard SD/MMC transactions, leaving the host drivers to implement only what is necessary to deal with their specific hardware. This also hooks the infrastructure into the PowerPC board code (similar to how the ethernet infrastructure now hooks in) Some of this code was contributed by Dave Liu <daveliu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
The current MMC infrastructure relies on the existence of an arch-specific header file. This isn't necessary, and a couple drivers were forced to implement dummy files to meet this requirement. Instead, we move the stuff in those header files into a more appropriate place, and eliminate the stubs and the #include of asm/arch/mmc.h Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
This is to get it out of the way of incoming MMC framework Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
MMC cards are not memory, so we stop treating them that way. Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Poonam_Aggrwal-b10812 提交于
This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: NPoonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
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由 Wolfgang Grandegger 提交于
The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory, CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module with "$ make TQM8548_AG_config". Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
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由 Wolfgang Grandegger 提交于
The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN interface. With NAND support, the image is significantly larger and TEXT_BASE is adjusted accordingly. U-Boot can be built for this module with "$ make TQM8548_BE_config". Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
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由 Wolfgang Grandegger 提交于
The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express. Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
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由 Peter Tyser 提交于
- Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Peter Tyser 提交于
Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Srikanth Srinivasan 提交于
Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: NSrikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: NTravis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Andy Fleming 提交于
Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Kumar Gala 提交于
When we introduced the 36-bit config of the MPC8572DS board we had the wrong PCI MEM bus address map. Additionally, the change to the address map exposes a small issue in our dummy read on the ULI bus. We need to use the new mapping functions to handle that read properly in the 36-bit config. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 12 2月, 2009 7 次提交
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由 Mike Frysinger 提交于
The Blackfin i2c driver has been rewritten thus the special ifdefs in the common code are no longer needed. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Heiko Schocher 提交于
With actual u-boot compiling the mgcoge port fails, because since commit ba705b5b it is necessary to define CONFIG_NET_MULTI. Seems to me the mgcoge port is the only actual existing 8260 port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed to be fixed. Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Adam Graham 提交于
The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: NAdam Graham <agraham@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB. It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx boards right now. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Jerry Van Baren 提交于
At some point an intentional double space at the end of the sentence got changed into a tab in the GPL header line: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the This patch fixes the damage. Signed-off-by: NGerald Van Baren <vanbaren@cideas.com>
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由 Heiko Schocher 提交于
If on your board is more than one flash, you must know the size of every single flash, for example, for updating the DTS before booting Linux. So make this function flash_get_info() extern, and you can have all info about your flashes. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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- 10 2月, 2009 10 次提交
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由 Ben Warren 提交于
Added new CONFIG options for the three type of MAC-PHY interconnect and applied them all relevant board config files Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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由 Kumar Gala 提交于
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NStefan Roese <sr@denx.de>
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由 Kumar Gala 提交于
We have common defines that we duplicate in various ways. Having an arch specific config.h gives us a common location for those defines. Eventually we should be able to replace this when we have proper Kconfig support. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Becky Bruce 提交于
Now that the rest of u-boot can support it, change the PCI bus address of the PCI MEM regions from 0x80000000 to 0xc0000000, and use the same bus address for both PCI1 and PCI2. This will maximize the amount of PCI address space left over to map RAM on systems with large amounts of memory. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Becky Bruce 提交于
Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Becky Bruce 提交于
Clean up PCI mapping concepts in the 8641 config - rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Becky Bruce 提交于
If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Becky Bruce 提交于
The BAT fields are architected; there's no need for these to be in cpu-specific files. Drop the duplication and move these to include/asm-ppc/mmu.h. Also, remove the BL_xxx defines that were only used by the alaska board, and switch to using the BATU_BL_xxx defines used by all the other boards. The BL_ defines previously in use had to be shifted into the proper position for use, which was inefficient. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Becky Bruce 提交于
It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Becky Bruce 提交于
If the VA and PA of the flash aren't the same, the banks list should be initialized to hold the physical address. Correct this. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
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- 08 2月, 2009 1 次提交
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由 Kumar Gala 提交于
The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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