The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

This is not used anywhere, so drop it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The debug print is missing a newline, add it.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

- Assorted minor fixes:
  - ARM: qemu-arm: enable USB boot in distro boot with UEFI
  - image: fdt: handle coalesced reserve region
  - cmd: thordown: Fix spelling of download.
  - fdt: Fix FIT header verification in mkimage and conduct same checks
    as bootm
  - test: Update test-imagetools.sh to match new syntax

With this patch which adds a removable USB mass storage to a list
of bootable devices, USB boot is supported in distro boot if UEFI is
configured.
Signed-off-by: NAKASHI Takahiro <takahiro.akashi@linaro.org>

Handle in boot_fdt_reserve_region
any return value > 0 of lmb_reserve() function;
it occurs when coalesced region are found:
adjacent reserved region are merged.

This patch avoid the error trace:
  ERROR: reserving fdt memory region failed..
when reserved region are merged (return value = 1).
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Signed-off-by: NVagrant Cascadian <vagrant@debian.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukasz Majewski <lukma@denx.de>

FIT header verification in mkimage was treating a return code as a boolean,
which meant that failures in validating the fit were seen as successes.

Additionally, mkimage was checking all formats to find a header which
passes validation, rather than using the image type specified to
mkimage.

checkpatch.pl checks for lines ending with '(' and alignment matching
open parentheses are ignored to keep with existing coding style.
Signed-off-by: NJordan Hand <jorhand@microsoft.com>

The syntax of dumpimage was simplified in commit 12b83187 ("tools:
dumpimage: Simplify arguments"), but the test
(test/image/test-imagetools.sh) was not updated and is now failing.

Update the test to use the new syntax.
Reported-by: NVagrant Cascadian <vagrant@debian.org>
Signed-off-by: NMartyn Welch <martyn.welch@collabora.com>
Tested-by: NVagrant Cascadian <vagrant@debian.org>

This pull request contains bugfixes for rcar_i2c, rcar_ii2c and
i2c_cdns driver.

Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek
is a bugfix for arm64 builds, as discussed with Marek on list.

Cosmetic change.  Any call to the recover function would need to do the
same check afterwards, so it's sensible to make it part of the function.
Signed-off-by: NIsmael Luceno <ismael.luceno@silicon-gears.com>

It needs to be done for both reads and writes, so do it at rcar_i2c_xfer
to avoid duplication.
Signed-off-by: NIsmael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Fix rcar_i2c_xfer return value, previously it was always returning
-EREMOTEIO when dealing with errors from calls to the read/write
functions.
Signed-off-by: NIsmael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Do the reset before clearing the MSR, otherwise it may result in a read
or write operation instead if the start condition is repeated.
Signed-off-by: NIsmael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Document the meaning of macros related to registers and values to be
written to them.
Signed-off-by: NIsmael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Setting up the delay only needs to be done once; move it to
rcar_i2c_set_speed so it's done at initialization time.
Signed-off-by: NIsmael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This patch adds support for handling arbitration lost
in case of multi master mode. When an arbitration lost
is detected, it retries for 10 times before failing.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

The arbitration lost interrupt was not getting cleared
while clearing interrupts. This patch fixes this by adding
arbitration lost interrupt as well during clear. This patch
also removes hardcoded value and defined a macro for it.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Add support for R-Car Gen3 SoCs into the driver, which encompases
the Gen3 SoC extra timing register handling and 64bit build fixes.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Read ICSR only once to avoid missing interrupts. This happens on R8A7791
Porter during reset, when reading the PMIC register 0x13, which may fail
sometimes because of the missed DTE interrupt.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: NHeiko Schocher <hs@denx.de>

- dw spi include file fix
- Allwinner A31 spi, been in ML in many releases.

Pull request for the UEFI subsystem for v2019.04-rc4

This pull request contains only bug fixes.

The most notable bug fixed was writing to random memory addresses when
trying to add a HII package of a yet unsupported package type.

Signed-off-by: NTom Rini <trini@konsulko.com>

- Assorted PFC fixes

First set of u-boot-atmel fixes for 2019.04 cycle

- Enable DHCP as boot-source in distro boot for NXP layerscape
  platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet

Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.

Also update the function, variable, structure names in driver from
sun4i into sunxi.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

- drop unused macros.
- use base instead of base_addr, for better code readability
- move .probe and .ofdata_to_platdata functions in required
  places to add platdata support in future.
- use sentinel sun4i_spi_ids.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

The usual SPI transmission protocol in Allwinner A10 and A31
controllers share similar context with minimal changes in register
offsets along with few additional register bits on A31.

So, add A31 spi controller support in existing sun4i_spi with A31
specific register offsets and bits.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.

Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.

So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.

This patch would also do that change, by enable and disable clock in
proper order.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.

Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.

Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204

Update the existing register writes using setbits_le32 and
clrbits_le32 in required places.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
  supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
  Allwinner SoCs.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

To drain rx fifo the fifo need to poll for how much data has
been filled up in rx fifo.

To achieve this, the current code is using wait_for_bit logic
on control register with exchange burst mode mask, which is not
a proper way of waiting for fifo filled up.

So, add code for polling rxfifo to be filled up using fifo
status register.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.

The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.
Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

SPL_GENERATE_ATMEL_PMECC_HEADER will generate a header for the SPL for NAND
information. The initial stage 1 bootloader will use this header in case the
NAND flash doesn't support commands to retrieve sector size, etc.
However this header is bad for different boot media, like MMC or SPI.
In case SD_BOOT or SPI_BOOT is used, remove the config for this.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>