The following error has been observed on i.MX25 with a high-speed SDSC
card:
    Data Write Failed in PIO Mode.

It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
because this bit takes 15 ms to be set after writing the first block to
DATPORT with this card. Without this timeout, all the blocks are
properly written.

This timeout was implemented by decrementing a variable, so it was
depending on the CPU frequency. Fix this issue by setting this timeout
to a long enough absolute duration (500 ms).
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable driver model for MMC (including BLK), SATA and USB. Note that USB
does not yet work correctly since the nodes are disabled. Hopefully this
can be resolved by the maintainer.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This driver does not currently support CONFIG_DM_MMC_OPS. Update it to
fully convert it to driver model.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Update this driver to support a live device tree.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We want to use fsl_esdhc_init() with driver model. Move the mmc_init() out
of this function so that we can use it for our common init.
Signed-off-by: NSimon Glass <sjg@chromium.org>

With driver model we want to store the mmc and configuration structure in
platform data. Set up structure up and use it for non-DM as well.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Since esdhc_init_common() can fail it should return an error code. Update
this and also adjust the timeout mechanism to use get_timer(), which is a
more common approach.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Since esdhc_reset() can fail it should return an error code. Update this
and also adjust the timeout mechanism to use get_timer(), which is a more
common approach.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Driver model wants to use the core functions in this file but accesses the
driver-private data in a different way. Move the code into new 'common'
functions and set up stubs to call these. Also sort the operations into
alphabetical order for consistency.
Signed-off-by: NSimon Glass <sjg@chromium.org>

With driver model we will not use mmc->priv to access driver-private data.
To accomodate this, update internal functions so that we can pass the
private data directly. This will allow the caller to obtain it as it
prefers.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We shouldn't always change the status to okay.  There could be
situations that the esdhc is intentionally disabled in the device
tree.
Signed-off-by: NLi Yang <leoyang.li@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.
Signed-off-by: NYork Sun <york.sun@nxp.com>

CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method
to set I/O to 1.8. To boards that does not support vqmmc-supply,
use vs18_enable in fsl_esdhc_cfg. If regulator is supported,
use fixed 1.8V regulator for vqmmc-supply.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Handle vqmmc supply. Some boards have a fixed I/O voltage
at 1.8V for emmc, so the usdhc also needs to be configured
as 1.8V by setting VSELECT bit. The vs18_enable is the one
that used to checking whether setting VSELECT or not in
the driver. So if vqmmc supply is 1.8V, set vs18_enable,
the driver will set VSELECT.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.

This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.

We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: NTom Rini <trini@konsulko.com>

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Don't build non DM_MMC code when DM_MMC defined so move
them into #ifndef CONFIG_DM_MMC

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
can divide by up to 512. Allow both of these settings.

The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
this change makes it possible to get 48 MHz from the USB PLL
(240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
(240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Signed-off-by: NBenoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Add compatible property for i.MX7ULP.
Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>

At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move fdt fixup of 'status' property into a weak function. This allows
board to define 'status' fdt fixup by themselves.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

To maintain consistency, set_ios type of legacy mmc_ops changed to int.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>

Need to initialize mmc->dev when probe, or will met
"dev_get_uclass_priv: null device", when `mmc dev 1`.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NMinkyu Kang <mk7.kang@samsung.com>

"mmc.h" is already included. It's duplicated.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.

Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.

If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
   implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
   external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add initial support for NXP's S32V234 SoC and S32V234EVB board.

The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.

Code originally writen by:
Original-signed-off-by: NStoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: NMihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: NEddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: NEddy Petrișor <eddy.petrisor@nxp.com>

In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Support Driver Model for fsl esdhc driver.

1. Introduce a new structure struct fsl_esdhc_priv
2. Refactor fsl_esdhc_initialize which is originally used by board code.
   - Introduce fsl_esdhc_init to be common usage for DM and non-DM
   - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part.
   - The original API for board code is still there, but we use
     'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it.
3. All the functions are changed to use 'struct fsl_esdhc_priv', except
   fsl_esdhc_initialize.
4. Since clk driver is not implemented, use mxc_get_clock to geth
   the clk and fill 'priv->sdhc_clk'.

Has been tested on i.MX6UL 14X14 EVK board:
"
=>dm tree
....
 simple_bus  [ + ]    |   `-- aips-bus@02100000
  mmc        [ + ]    |       |-- usdhc@02190000
  mmc        [ + ]    |       |-- usdhc@02194000
....
=> mmc list
FSL_SDHC: 0 (SD)
FSL_SDHC: 1 (SD)
"
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Hector Palacios <hector.palacios@digi.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-By: NEric Nelson <eric@nelint.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need
to be set an Abort command type when they are sent. So, we remove all
chip-specific #ifdefs and make it available for all platforms.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The MMC spec says "It is strongly recommended for hosts to implement
more than 500ms timeout value even if the card indicates the 250ms
maximum busy length."  Even the previous value of 300ms is known to
be insufficient for some cards. So, increase the timeout to 500ms.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The low four bits of the SYSCTL register are reserved on the USDHC
controller on i.MX6 and i.MX7 processors, but are used for clocking
operations on earlier models.

Guard against their usage by hiding the bit mask macros on those
processors.

These bits are used to prevent glitches when changing clocks on
i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7.

>From the i.MX6DQ RM:
	To prevent possible glitch on the card clock, clear the
	FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS
	or DVS in System Control Register) or setting RSTA bit.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Reviewed-by: NHector Palacios <hector.palacios@digi.com>

When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

If adapter card type identification is supported for platform, we would
enable dat[4:7] for eMMC4.5 Adapter Card.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>