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  1. 15 5月, 2012 4 次提交
  3. 30 4月, 2012 5 次提交
  5. 25 4月, 2012 5 次提交
    • T
      powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot · 5d065c3e
      由 Timur Tabi 提交于 
      Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time.  The board-specific code is
deleted.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      5d065c3e
    • L
      powerpc/corenet_ds: Slave uploads ucode when boot from SRIO · 3f1af81b
      由 Liu Gang 提交于 
      When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      3f1af81b
    • L
      powerpc/corenet_ds: Slave module for boot from SRIO · 292dc6c5
      由 Liu Gang 提交于 
      For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
      292dc6c5
    • Y
      powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards · 1ba62f10
      由 York Sun 提交于 
      P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      1ba62f10
    • C
      powerpc/p1023rds: Disable nor flash node and enable nand flash node · 617e46e3
      由 Chunhe Lan 提交于 
      In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.

Default device tree nor and nand node should have the following structure:

	Example:

		nor_flash: nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x02000000>;
			bank-width = <2>;
			device-width = <1>;
			status = "okay";

			partition@0 {
				label = "ramdisk";
				reg = <0x00000000 0x01c00000>;
			};
		}

		nand_flash: nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1023-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x00040000>;
			status = "disabled";

			u-boot-nand@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				read-only;
			};
		}

When booting from nor flash, the status of nor node is enabled and the
status of nand node is disabled in the default dts file, so do not do
anything.

But, when booting from nand flash, need to do some operations:

	o Disable the NOR node by setting status = "disabled";
	o Enable the NAND node by setting status = "okay";
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      617e46e3
  7. 22 4月, 2012 1 次提交
  9. 18 4月, 2012 1 次提交
  11. 17 4月, 2012 2 次提交
  13. 16 4月, 2012 5 次提交
  15. 04 4月, 2012 3 次提交
  17. 01 4月, 2012 1 次提交
  19. 31 3月, 2012 1 次提交
  21. 30 3月, 2012 1 次提交
  23. 29 3月, 2012 11 次提交