Fix:
fpga.c: In function 'fpga_pre_fn':
fpga.c:88:16: warning: variable 'reg' set but not used
[-Wunused-but-set-variable]
nand.c: In function 'alpr_nand_dev_ready':
nand.c:125:18: warning: variable 'val' set but not used
[-Wunused-but-set-variable]
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: NStefan Roese <sr@denx.de>

* 'sr@denx.de' of git://git.denx.de/u-boot-staging:
  image: Don't detect XIP images as overlapping.
  image: Implement IH_TYPE_KERNEL_NOLOAD

* 'master' of git://git.denx.de/u-boot-ppc4xx:
  ppc4xx: Add Io64 board support
  ppc4xx: fix PMC440 painit command
  ppc4xx: remove invalid access to PCI_BRDGOPT2 register
  ppc4xx: use CONFIG_PCI_BOOTDELAY instead of private implementation

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  mpc85xx: support for Freescale COM Express P2020
  arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning
  mpc85xx: support board-specific reset function
  powerpc/85xx: verify the localbus device tree address before booting the OS
  mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification
  powerpc/p3060qds: Add board related support for P3060QDS platform
  powerpc/85xx: clean up and document the QE/FMAN microcode macros
  powerpc/85xx: always implement the work-around for Erratum SATA_A001
  powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h
  powerpc/85xx: Add workaround for erratum A-003474
  powerpc/85xx: fixup flexcan device tree clock-frequency
  powerpc/85xx: Add workaround for erratum CPU-A003999

bootm_load_os() detects when it writes the decompressed image over
the top of the compressed image. If this happens, the original image
is corrupted. When the original image is a multi-component legacy image,
or a (potentially multi-component) FIT image, this implies that other
components may be corrupted. In turn, this means that booting is unlikely
to be successful.

However, in the case of no image compresssion coupled with an image with
load address equal to where the image is already located (e.g. an XIP
kernel, or IH_TYPE_KERNEL_ANYLOAD), there has been no copy and hence no
corruption, no matter whether it's a single-component legacy image, a
multi-component legacy image, or a FIT image. In this case, disable the
overlap detection, and allow boot to continue.

Without this change, when booting a single-component legacy image that
contains an IH_TYPE_KERNEL_ANYLOAD, bootm_load_os() would have returned
BOOTM_ERR_OVERLAP, but the caller ignores this, and boot continues and
succeeds. Now, the false error is no longer even returned.

Without this change, when booting a FIT image that contains an
IH_TYPE_KERNEL_ANYLOAD, bootm_load_os() would have returned
BOOTM_ERR_OVERLAP, which would then cause the caller to reset the board.
Now, the false error is no longer returned, and boot succeeds.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The legacy uImage format includes an absolute load and entry-point
address. When bootm operates on a kernel uImage in memory that isn't
loaded at the address in the image's load address, U-Boot will copy
the image to its address in the header.

Some kernel images can actually be loaded and used at any arbitrary
address. An example is an ARM Linux kernel zImage file. To represent
this capability, IH_TYPE_KERNEL_NOLOAD is implemented, which operates
just like IH_TYPE_KERNEL, except that the load address header is
ignored, and U-Boot does not copy the image to its load address, but
rather uses it in-place.

This is useful when sharing a single (uImage-wrapped) zImage across
multiple boards with different memory layouts; in this case, a specific
load address need not be picked when creating the uImage, but instead
is selected by the board-specific U-Boot environment used to load and
boot that image.

v2: Rename from IH_TYPE_KERNEL_ANYLOAD to IH_TYPE_KERNEL_NOLOAD.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Board support for the Guntermann & Drunck Io64.
Signed-off-by: NDirk Eibach <eibach@gdsys.de>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes the PMC440 BSP command painit. The implementation was
broken since the step to the new environment handling.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch removes an invalid call to pci_write_config_dword to
PCI_BRDGOPT2 register. This function must not be used from pci_target_init
and is also at the wrong place. The correct call is done later in
pci_target_init via pci_hose_write_config_dword.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch switches PMC440 board code to the CONFIG_PCI_BOOTDELAY option
instead of using a private implemention. This relies on Anatolji's patch
that moves the pcidelay handling behind pci_target_init.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).
Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Fix:

interactive.c: In function 'fsl_ddr_interactive':
interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable]
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR.  If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.

Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong.  This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.
Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P3060QDS is a Freescale reference board for the six-core P3060 SOC.

P3060QDS Board Overview:
 Memory subsystem:
  - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
  - 128M Bytes NOR flash single-chip memory
  - 16M Bytes SPI flash
  - 8K Bytes AT24C64 I2C EEPROM for RCW
 Ethernet:
  - Eight Ethernet controllers (4x1G + 4x1G/2.5G)
  - Three VSC8641 PHYs on board (2xRGMII + 1xMII)
  - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
 PCIe: Two PCI Express 2.0 controllers/ports
 USB:  Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
 I2C:  Four I2C controllers
 UART: Supports two dUARTs up to 115200 bps for console
 RapidIO:  Two RapidIO, sRIO1 and sRIO2
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman.  Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both.  A given SOC will only have
a QE or an Fman, so this is safe.

Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND.  There's no way to know by looking at a variable how it's supposed
to be used.

In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default.  So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA
controller, so it should be defined in config_mpc85xx.h instead of the various
board header files.  So now CONFIG_FSL_SATA_V2 is always defined on the P1013,
P1022, P2041, P3041, P5010, and P5020.  It was already defined for the
P1010 and P1014.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Erratum A-003474: Internal DDR calibration circuit is not supported

Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.

Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
	CCSRBAR + DDR OFFSET + 0xf54
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Make the fixup matchable with dts and kernel.  Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency".  We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.

We now keep the old interfaces to make previous kernel work. They should
be removed in the future.
Signed-off-by: NJia Hongtao <B38951@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Erratum A-003999: Running Floating Point instructions requires special
initialization.

Impact:
Floating point arithmetic operations may result in an incorrect value.

Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

If no controller is present, the i8402 driver should return immediately and
not attempt to operate on the missing hardware.

In kbd_input_empty, the status register is checked every millisecond to see
whether the input buffer is empty, up to a timeout which is tracked by
decrimenting a counter each time the check is performed. The decrement is
performed with a postfix -- operator, and the value of the counter is
checked in place. That means that when the counter reaches zero and the
loop terminates, it will actually be decrimented one more time and become
-1. That value is returned as the return value of the function. That would
give the right answer if it wasn't for that extra decrement because a
timeout would indicate that the buffer never became empty.

This change fixes both of those bugs.
Signed-off-by: NGabe Black <gabeblack@chromium.org>

Signed-off-by: NGabe Black <gabeblack@chromium.org>

When gcc compiles some 64 bit operations on a 32 bit machine, it generates
calls to small functions instead of instructions which do the job directly.
Those functions are defined in libgcc and transparently provide whatever
functionality was necessary. Unfortunately, u-boot can be built with a
non-standard ABI when libgcc isn't. More specifically, u-boot uses
-mregparm. When the u-boot and libgcc are linked together, very confusing
bugs can crop up, for instance seemingly normal integer division or modulus
getting the wrong answer or even raising a spurious divide by zero
exception.

This change borrows (steals) a technique and some code from coreboot which
solves this problem by creating wrappers which translate the calling
convention when calling the functions in libgcc. Unfortunately that means
that these instructions which had already been turned into functions have
even more overhead, but more importantly it makes them work properly.

To find all of the functions that needed wrapping, u-boot was compiled
without linking in libgcc. All the symbols the linker complained were
undefined were presumed to be the symbols that are needed from libgcc.
These were a subset of the symbols covered by the coreboot code, so it was
used unmodified.

To prevent symbols which are provided by libgcc but not currently wrapped
(or even known about) from being silently linked against by code generated
by libgcc, a new copy of libgcc is created where all the symbols are
prefixed with __normal_. Without being purposefully wrapped, these symbols
will cause linker errors instead of silently introducing very subtle,
confusing bugs.

Another approach would be to whitelist symbols from libgcc and strip out
all the others. The problem with this approach is that it requires the
white listed symbols to be specified three times, once for objcopy, once so
the linker inserts the wrapped, and once to generate the wrapper itself,
while this implementation needs it to be listed only twice. There isn't
much tangible difference in what each approach produces, so this one was
preferred.
Signed-off-by: NGabe Black <gabeblack@chromium.org>

The new implementation is about twice as fast as the old. This is from
glibc-2.14, sysdeps/i386/memset.c.
Signed-off-by: NGabe Black <gabeblack@chromium.org>

Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

This change adds an upper bound for symbols which are fixed up after u-boot
is relocated into RAM. This way portions that are left at their original
location can be referred to without having to manually fix up any pointers.
Signed-off-by: NGabe Black <gabeblack@chromium.org>

There are two blobs embedded into the u-boot image which are linked to run
at an address which is different from where they actually end up in the
ROM, one called "realmode" and one called "bios". There are realmode_setup
and bios_setup functions which prepare those blobs by copying them into the
location they're supposed to run from, among other things.

During u-boot relocation from ROM to RAM, the text and a few data segments
are copied over. The realmode and bios sections are not copied, and so the
only place they can be read from is their original location in the ROM.
Looking specifically at the bios blob, there are symbols defined in the
linker script called __bios_start and __bios_size which are defined to be
the start and size of the blob in the ROM.

In the bios_setup function, there seem to be two mistakes happening. First,
the offset from ROM to RAM is being added to __bios_start which implies that
this code expects to use the copy moved to RAM. No such copy is made, so
that's wrong. More subtly, when u-boot relocates itself, it goes through
all of the relocations stored in .rel.dyn and fixes them up. This has the
effect of transforming the __bios_start reference in bios_setup so that it
refers to the version in RAM (if one existed) instead of the one in ROM. To
correct for that, the offset actually needs to be subtracted out again to
translate the address back into the ROM.

The net effect is that for both blobs, a + needs to be changed to a -.
Signed-off-by: NGabe Black <gabeblack@chromium.org>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Some CPUs have strict alignment requirements for these tables
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Planned future ports requires more granularity for some options
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

By adding a multiboot header, U-Boot can be loaded by GRUB2. Using GRUB2 to
bootstrap U-Boot is useful for using an existing BIOS to get an initial
U-Boot port up and running before implementing the low-level reset vector
code, SDRAM init, etc. and overwriting the BIOS
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Nobody uses them anyway
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
Acked-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>

Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>