move CONFIG_BOOTDELAY into a Kconfig option. Used for this
purpose the moveconfig.py tool in tools.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

Unlike NAND, eMMC can be re-written without erasing.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
from an eMMC device.  They are useful to reduce the memory footprint
of SPL, rather than compiling the whole MMC framework.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Avoid use of hard coded mmcdev value, use bootpart
instead, so finduuid works based on bootpart set
for a specific platform.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Now that all Keystone2 dts file names are changed in Linux kernel, reflect the
same in evn variables inorder to find the right dtb file.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

There is new strider cpu flavor with DisplayPort video.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NTom Rini <trini@konsulko.com>

There is a new strider console flavor with DisplayPort
video.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NTom Rini <trini@konsulko.com>

Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.

Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>

When the CONFIG_BOOTP_SERVERIP option is set, we ignore all
dhcp values for the tftp server and use our own serverip and
file name instead.

This is usually not what we want and I doubt it's set for a
good reason on ZynqMP. It definitely hurts if we want to support
uEFI PXE boot on it. So just remove the option for now.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify zcu102 board file by moving CONFIG_AHCI enabling to common
file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

zc1751-dc4 contains four GEMs.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Phys are available on zc1751-dc4 that's why enable them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify board file by enabling CMD_NAND via Kconfig.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Create an entry for "config USB_XHCI_DWC3" in Kconfig and
switch over to it for all boards.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move CONFIG_USB_XHCI to defconfig files for all boards, renaming it
into CONFIG_USB_XHCI_HCD.

As commented in the help of "config USB_XHCI" entry, this has been
a TODO for a long time; now CONFIG_USB_XHCI_HCD and CONFIG_USB_XHCI
have been unified in favor of the former.

Note:
Some boards define CONFIG_USB_XHCI in their headers without
CONFIG_USB, which does not meet the "depends on" in Kconfig.
I added CONFIG_USB=y for those boards when converting.
Otherwise, they would fail to build.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These Blackfin boards are the last ones that define CONFIG_USB in
their headers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This fixes the last remaining libgcc warning, where the symbol was
defined twice.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Before this patch, when booting from MMC (no filesystem), the SPL
loaded U-Boot from a fixed offset.
It will now load U-Boot from an offset of 256kB (which is 4 times the
padded SPL image) in the third partition.

This behaviour is similar to what the vendor SPL (based on
U-Boot 2013.01) does, and allows to directly 'dd' the
u-boot-with-spl.sfp file to the A2 partition.
Signed-off-by: NSylvain Lesne <lesne@alse-fr.com>

Somehow the sr1500 is missing this comma in the CONFIG_BOOTARGS
definition. This patch adds it to.
Signed-off-by: NStefan Roese <sr@denx.de>
Reported-by: NPavel Machek <pavel@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>

Enable both features to reduce the SPL size by 6 kiB.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>

Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
 - 1 GiB of DRAM
 - 1 Gigabit ethernet
 - 1 USB gadget port
 - 1 USB host port with an on-board hub
 - 2 QSPI NORs connected to the Cadence QSPI core
 - Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request

P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B
port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion
headers.

Currently, due to U-Boot's level of support for Tegra186, the only
features supported by U-Boot are the console UART and the on-board eMMC.
Additional features will be added over time.

U-Boot has so far been tested by replacing the kernel image on the device
with a U-Boot binary. It is anticipated that U-Boot will eventually
replace the CCPLEX bootloader binary, as on previous chips. This hasn't
yet been tested.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This adds the bare minimum code to support Tegra186, with UART and eMMC
working.

The empty gpio.h is required because <asm/gpio.h> includes it. A future
cleanup round may be able to solve this for all Tegra generations at once.

mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but
instead to defer everything to mach-tegra/tegra186/Makefile. This allows
the SoC code to pick-and-choose which of the C files in the "common"
mach-tegra/ directory to compile in based on the SoC's needs. Most of the
code is not valid for Tegra186, and this approach removes the need for
mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach
may be applied to all other Tegra SoCs in a future cleanup round.

board186.c is introduced to replace board.c and board2.c. These files
currently contain a slew of SoC- and board-specific code that is not
valid for Tegra186. This approach avoids adding yet more ifdefs to those
files. A future cleanup round may refactor most of board*.c into board-/
SoC-specific functions files thus allowing the top-level functions like
board_init_early_f to be shared again.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Future chips will contain different GPIO HW. This change will enable
future SoC support to select the appropriate GPIO driver for their HW,
in a future-looking fashion, using Kconfig.

TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all
current Tegra chips used this GPIO HW) to simplify the later addition
of support for Tegra SoCs that use different GPIO HW.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Change bootm flash address and mtd partition table for 8MB flash profile.
Signed-off-by: NWills Wang <wills.wang@live.com>

Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>

Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>

As the old ethernet PHY is not available any more, the x600 board has
been redesigned with the Micrel KSZ9031 PHY. This patch adds support
to autodetect the PHY and configure the Micrel PHY correctly.
Signed-off-by: NStefan Roese <sr@denx.de>

Populate the right dtb file and console for AM335x-ICEv2 board.
Reviewed-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

In order to enable cpsw on AM335x ICEv2 board, the following needs to be done:

1)There are few on board jumper settings which gives a choice between
cpsw and PRUSS, that needs to be properly selected[1]. Even after selecting
this, there are few GPIOs which control these muxes that needs to be held high.

2) The clock to PHY is provided by a PLL-based clock synthesizer[2] connected
via I2C. This needs to properly programmed and locked for PHY operation.
And PHY needs to be reset before before being used, which is also held by
a GPIO.

3) RMII mode needs to be selected.

[1] http://www.ti.com/lit/zip/tidr336
[2] http://www.ti.com/lit/ds/symlink/cdce913.pdfReviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Re-org env sections so that we can fall back to env is in FAT on SD
card, for broader board compatibility
Signed-off-by: NTom Rini <trini@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

This follows on from commit d98b0523 ("powerpc: Cleanup BOOTFLAG_*
references") and commit fc3d2976 ("Drop bogus BOOTFLAG_* definitions").
Remove the definitions that have crept in since.
Signed-off-by: NChris Packham <judge.packham@gmail.com>

Updated the CONFIG_SPL_TEXT_BASE to support secure parts (moving
the start address past secure reserved memory and the size of the
security certificate that precedes the boot image on secure devices).
Updated the related CONFIG_SPL_MAX_SIZE to properly reflect the
internal memory actually available on the various device flavors
(Common minimum internal RAM guaranteed for various flavors of
DRA7xx/AM57xx is 512KB).
Signed-off-by: NDaniel Allred <d-allred@ti.com>
Signed-off-by: NMadan Srinivas <madans@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Adds code to detect AM43xx HS EVMS - the string in the
I2C EEPROM for HS EVMs differs from GP EVMs. Adds code to
for evm detection, regardless of whether the evm is for
GP or HS parts, and updates board init to use that.

Modifies findfdt command to pick up am437x-gp-evm.dtb for
the HS EVMs also, as the boards are similar except for
some security specific changes around power supply and
enclosure protection.
Signed-off-by: NMadan Srinivas <madans@ti.com>
Signed-off-by: NDaniel Allred <d-allred@ti.com>
Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com>
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Updates configs/am43xx_evm.h to use CONFIG options from
SOC specific Kconfig file for various calculations.

On AM43x devices, the address of SPL entry point  depends on
the device type, i.e. whether it is secure or non-secure.

Further, for non-secure devices, the SPL entry point is different
between  USB HOST boot mode, other "memory" boot modes (MMC, NAND)
and "peripheral" boot modes (UART, USB)

To add to the complexity, on secure devices, in addition to the
above differences, the SPL entry point can change because of the
space occupied by other components (other than u-boot or spl)
that go into a secure boot image.

To prevent the user from having to modify source files every time
any component of the secure image changes, the value of
CONFIG_SPL_TEXT_BASE has been set using a Kconfig option that
is supplied in the am43xx_*_defconfig files

Using the CONFIG options also enables us to do away with some
compile time flags that were used to specify CONFIG_SPL_TEXT_BASE
for different boot modes.

On QSPI devices, the same problem described above occurs w.r.t. the
address of the u-boot entry point in flash, when booting secure
devices. To handle this, CONFIG_SYS_TEXT_BASE is also setup via
a Kconfig option and the defconfig files.
Signed-off-by: NMadan Srinivas <madans@ti.com>
Signed-off-by: NDaniel Allred <d-allred@ti.com>
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
Tested-by: NAndreas Dannenberg <dannenberg@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Adding support for AM43xx secure devices require the addition
of some SOC specific config options like the amount of memory
used by public ROM and the address of the entry point of u-boot
or SPL, as seen by the ROM code, for the image to be built
correctly.

This mandates the addition of am AM43xx CONFIG option and the
ARM Kconfig file has been modified to source this SOC Kconfig
file. Moving the TARGET_AM43XX_EVM config option to the SOC
KConfig and out of the arch/arm/Kconfig.

Updating defconfigs to add the CONFIG_AM43XX=y statement and
removing the #define CONFIG_AM43XX from the header file.
Signed-off-by: NMadan Srinivas <madans@ti.com>
Signed-off-by: NDaniel Allred <d-allred@ti.com>
Tested-by: NAndreas Dannenberg <dannenberg@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>