- 07 6月, 2017 40 次提交
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由 Andy Yan 提交于
Add clock driver support for Rockchip rv1108 soc Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
Add pinctrl support for Rockchip rv1108 soc Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
Add support to mkimage for rv1108 soc, the max spl code size for rv1108 is 6kb, and the spl code should be packed by rksd, wether boot from emmc or spi nor flash. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
For the RK3399-Q7 module, we use full OF_CONTROL (i.e. not OF_PLATDATA) for SPL. In this configuration, the rockchip_dw_mmc driver retrieves one of its clocks via clk_get_by_name and fails if this is not possible. For this reason, we can not filter clock-names from the device-tree nodes used for the configuration of the SPL stage. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The RK3399-Q7 exposes I2C on its edge connector and uses it as one of the interfaces towards the on-module STM32 (for the emulated RTC and fan-controller). Enable I2C and CMD_I2C support in the defconfig. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The RK3399-Q7 has a KSZ9031 GbE PHY. Enable support for it in defconfig. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
On the RK3399-Q7, we need PMIC support (for the RK808) to enable HDMI output, as one of the required powerrails is not enabled on boot. For this, we need to enable the RK808 driver. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Version-changes: 3 - With the recent upstream changes to the RK808 (PMIC) driver, the associated configuration options have been renamed to RK8XX. Track this change in the RK3399-Q7 defconfig. Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Klaus Goger 提交于
defines the spl-payload to 256k (0x40000) Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
On the RK3399-Q7, the on-module USB3 hub is held in reset at boot-up to save power and needs to be woken up using GPIO4A3. Note that this is not a negated reset-signal (due to a level shifter being needed for this signal anyway), but a negated enable-signal: to enable, we need to output LOW (i.e. 0)... so we mark this as an ACTIVE_LOW signal. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built with the DDR3-1866 option. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866), if the PCB layout permits and appropriate memory timings are used. This changes the sanity checks to allow a DTS to request DDR3-1866 operation. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Philipp Tomsich 提交于
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to clearly state a timeout in milliseconds and use get_timer (based on the ARMv8 architected timer) to detect a timeout. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
This change restores the earlier setting of init_boot_size to include the maximum area covered by the the boot ROM of each chip for resolve issues with back-to-bootrom functionality reported by Kever and Heiko. To ensure that we don't run into the same issue again in the future, I have updated the comments accordingly and added a reference to the mailing list archive (there's some very helpful info from Andy Yan that provides background on the BootROM requirements regarding these fields). See https://lists.denx.de/pipermail/u-boot/2017-May/293267.html for some background (by Andy Yan) of how the BootROM processes this field. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The Rockchip BootROM relies on init_size being aligned to 2KB (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html). This pads the image to 2KB both for SD card images and SPI images and uses a common symbolic constant for the alignment. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The rockchip image generation was previously missing the ability to verify the generated header (and dump the image-type) without having to resort to hexdump or od. Experience in our testing has showed it to be very easy to get the rkspi and rksd images mixed up and the lab... so we add the necessary support to have dumpimage tell us what image type we're dealing with. This change set adds the verify_header and print_header capability to the rksd/rkspi image drivers (through shared code in rkcommon). As of now, we only support images fully that are not RC4-encoded for the SPL payload (i.e. header1 and payload). For RC4-encoded payloads, the outer header (header0) is checked, but no detection of whether this is a SD/MMC or SPI formatted payload takes place. The output of dumpsys now prints the image type (spl_hdr), whether it is a SD/MMC or SPI image, and the (padded) size of the image: $ ./tools/dumpimage -l ./spl.img Image Type: Rockchip RK33 (SD/MMC) boot image ^^^^^^ SD/MMC vs. SPI indication ^^^^ spl_hdr indicated by the image Data Size: 79872 bytes Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Update maintainer to Kever Yang for William Zhang is not work for this board now. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Directory board/rockchip/ are all boards for Rockchip SoCs, so add it to maintained entry. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Send patch to Kever Yang instead of Lin Huang for Rockchip patches, for Lin is not always working on upstream U-Boot. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Changed , to : in subject: Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Meng Dongyang 提交于
Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Meng Dongyang 提交于
Add config of max root ports and add config to enable xhci controller. Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Meng Dongyang 提交于
Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Meng Dongyang 提交于
Add defconfig for usb and ehci and ohci controller, config maximal number of ports of the root hub for ohci driver. Signed-off-by: NMeng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
In rk3328, some function pin may have more than one choice, and muxed with more than one IO, for example, the UART2 controller IO, TX and RX, have 3 choice(setting in com_iomux): - M0 which mux with GPIO1A0/GPIO1A1 - M1 which mux with GPIO2A0/GPIO2A1 - usb2phy which mux with USB2.0 DP/DM pin. We should not decide which group to use in pinctrl driver, for it may be different in different board, it should goes to board file, and the pinctrl file should setting correct iomux depends on the com_iomux value. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Move GRF register bit definition into GRF header file, remove 'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
U-Boot prefer to use MASKs with SHIFT embeded, clean the Macro definition in grf header file and pinctrl driver. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
- hclk/pclk_div range should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Embeded the shift in mask MACRO definition in cru header file and clock driver. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
PX5 EVB is designed by Rockchip for automotive field with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS HDMI video input/output interface, audio codec ES8396, WIFI / BT (on RTL8723BS), Gsensor BMA250E and light&proximity sensor STK3410. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andreas Färber 提交于
The GeekBox is a TV box from GeekBuying, based on an MXM3 module. The module can be used with base boards such as the GeekBox Landingship. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
Sheep board is designed by Rockchip as a EVB for rk3368. Currently it is able to boot a linux kernel and system to console with the miniloader run as fist level loader. Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
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由 Andy Yan 提交于
Add sysreset driver to reset rk3368 SOC. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andreas Färber 提交于
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
Add driver to support iomux setup for the most commonly used peripherals on rk3368. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Mark Kettenis 提交于
Since priv->init_voltage is an unsigned integer it can never be negative. So the current code fails to detect a missing 'regulator-init-microvolt' property and instead misconfigures the PWM device. Fix this by making the relevant members of 'struct pwm_regulator_info' signed integers. Signed-off-by: NMark Kettenis <kettenis@openbsd.org>
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由 Heiko Stübner 提交于
Till now get_ldo_reg did a return &rk808_ldo[num - 1]; to return the ldo register offset but didn't take into account that its calling functions already created the ldo as ldo = dev->driver_data - 1. This resulted in the setting for ldo8 writing to the register of ldo7 and so on. So fix this and get the correct ldo register data. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With everything in place (i.e. the new efuse driver, the clk-support for the non-secure efuse block, and the board-specific functions to derive 'serial#' from the cpu-id within the efuses), enable this in the RK3399-Q7 defconfig. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Klaus Goger 提交于
Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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