- 21 6月, 2013 27 次提交
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由 Ying Zhang 提交于
There will need the environment in SPL for reasons other than network support (in particular, hwconfig contains info for how to set up DDR). Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT for environment in common/Makefile. Signed-off-by: NYing Zhang <b40530@freescale.com> Reviewed-by: NTom Rini <trini@ti.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ying Zhang 提交于
There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: NYing Zhang <b40530@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ying Zhang 提交于
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: NYing Zhang <b40530@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
PCIe TLB should be created with CONFIG_PCI defined Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
Relax parameters to give address latching more time to setup. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Scott Wood 提交于
Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Mingkai Hu 提交于
Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
T4 can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Liu Gang 提交于
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet file when the tabs are set to 8 characters. And the standard for u-boot should be 8 character tabs! So this issue should be amended. 2. Add a NOTE for the ENV parameters of the Slave. Signed-off-by: NLiu Gang <Gang.Liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Fabio Estevam 提交于
Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: NHeinz Wrobel <heinz.wrobel@freescale.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
BSC9132 has 3 IFC banks. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Priyanka Jain 提交于
BSC9131RDB has 1GB DDR. Out of this, only 880MB is passed on to Linux via bootm_size. Remaining -16MB is reserved for PowerPC-DSP shared control area -128MB is reserved for DSP private area. Also 256MB, out of this 880MB is required for data communication between PowerPC and DSP core. For this bootargs are modified to pass parameter to create 1 hugetlb page of 256MB via default_hugepagesz, hugepagesz and hugepages Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Priyanka Jain 提交于
BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Priyanka Jain 提交于
BSC9131RDB supports Sysclk -66MHz if jumper J16 is close (default state) -100MHz if jumper J16 is open Add targets -BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz -BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
- Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB, LAW entries as per NAND boot Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
- Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
- defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot - remove nand_spl support for P1010RDB Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Mingkai Hu 提交于
To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x80000000), it will be extended to 0xffffffff80000000 when phys_size_t is type 'unsigned long long'. Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
Accidentally applied an earlier version of the patch, which set the compatible to "fsl,qoriq-clockgen-2", lacking the final ".0". Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
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- 19 6月, 2013 1 次提交
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由 Jim Lin 提交于
If we try to boot from NET device, NetInitLoop in net.c will be invoked. If NET device is not installed, eth_get_dev() function will return eth_current value, which is NULL. When NetInitLoop is called, "eth_get_dev->enetaddr" will access restricted memory area and therefore cause hanging. This issue is found on Tegra30 Cardhu platform after adding CONFIG_CMD_NET and CONFIG_CMD_DHCP in config header file. Signed-off-by: NJim Lin <jilin@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com>
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- 17 6月, 2013 1 次提交
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由 Simon Glass 提交于
This error may not be defined on some platforms such as MacOS so host compilation will fail. Use one of the more common errors instead. Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NAndreas Bießmann <andreas.devel@googlemail.com> Tested-by: NLubomir Popov <lpopov@mm-sol.com>
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- 15 6月, 2013 1 次提交
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- 14 6月, 2013 10 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Stephen Warren 提交于
Use a negative value of CONFIG_ENV_OFFSET for all NVIDIA reference boards that store the U-Boot environment in the 2nd eMMC boot partition. This makes U-Boot agnostic to the size of the eMMC boot partition, which can vary depending on which eMMC device was actually stuffed into the board. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
A negative value of CONFIG_ENV_OFFSET is treated as a backwards offset from the end of the eMMC device/partition, rather than a forwards offset from the start. This is useful when a single board may be stuffed with different eMMC devices, each of which has a different capacity, and you always want the environment to be stored at the very end of the device (or eMMC boot partition for example). One example of this case is NVIDIA's Ventana reference board. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
Enhance the MMC core to calculate the size of each MMC partition, and update mmc->capacity whenever a partition is selected. This causes: mmc dev 0 1 ; mmcinfo ... to report the size of the currently selected partition, rather than always reporting the size of the user partition. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
Describe the meaning of CONFIG_ENV_IS_IN_MMC, and all related defines that must or can be set when using that option. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk> Acked-by: NTom Rini <trini@ti.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andrew Gabbasov 提交于
After waiting for the command completion event, the interrupt status bits, that occured to be set by that time, are cleared by writing them back. It is supposed, that it should be command related bits (command complete and may be command errors). However, in some cases the DMA already completes by that time before the full transaction completes. The corresponding DINT bit gets set and then cleared before even entering the loop, waiting for data part completion. That waiting loop never gets this bit set, causing the operation to hang. This is reported to happen, for example, for write operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II 8GB card. The solution could be to explicitly clear only command related interrupt status bits. However, since subsequent processing does not rely on any command bits state, it could be easier just to remove clearing of any bits at that point, leaving them all until all data processing completes. After that the whole register will be cleared at once. Also, on occasion, interrupts masking moved to before writing the command, just for the case there should be no chance of interrupt between the first command and interrupts masking. Reported-by: NDirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: NDirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Fabio Estevam 提交于
Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode) we see mx6 systems to hang after doing a 'save' command. Revert this commit since the original 'ifdef' logic from 7b43db92 (drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one. Reported-by: NTapani Utriainen <tapani@technexion.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ruud Commandeur 提交于
This patch fixes a bug related to mmc writes. When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting in an SD-Card that is no longer responding. It appears to be, that set_cluster can be called with a size being zero. That can be with a file that has a size being an exact multiple (including 0) of the clustersize, but also for files that are smaller than the size of one cluster. The same problem occurs if the "mmc write" command is given with a block count being 0. By adding a check for the block count being zero in mmc_write_blocks (drivers/mmc.c), this problem is solved. Signed-off-by: NRuud Commandeur <rcommandeur@clb.nl> Cc: Tom Rini <trini@ti.com> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Mats Karrman <Mats.Karrman@tritech.se> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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CAP register don't have any information for 8-bit buswidth support on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information. Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using mmc_set_bus_width even if controller doesn't support. Below change has code information. "mmc: Properly determine maximum supported bus width" (sha1: 7798f6db) Bug log: <mmc plus and emmc cards) ------- zynq-uboot> mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: fe ..... So enable 8-bit support only for 3.0 spec using CAP and for below 3.0 assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver if host have a support. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Bo Shen 提交于
The commit d196bd88 (env_mmc: add support for redundant environment) introduce the following compile error when enable redundant environment support with MMC ---8<--- env_mmc.c:149: error: 'env_t' has no member named 'flags' env_mmc.c:248: error: 'env_t' has no member named 'flags' env_mmc.c:248: error: 'env_t' has no member named 'flags' env_mmc.c:250: error: 'env_t' has no member named 'flags' env_mmc.c:250: error: 'env_t' has no member named 'flags' env_mmc.c:252: error: 'env_t' has no member named 'flags' env_mmc.c:252: error: 'env_t' has no member named 'flags' env_mmc.c:254: error: 'env_t' has no member named 'flags' env_mmc.c:254: error: 'env_t' has no member named 'flags' env_mmc.c:267: error: 'env_t' has no member named 'flags' make[1]: *** [env_mmc.o] Error 1 --->8--- Add this patch to fix it Signed-off-by: NBo Shen <voice.shen@atmel.com> Reviewed-by: NMichael Heimpold <mhei@heimpold.de> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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